XC5VSX95T-1FF1136C Xilinx Inc, XC5VSX95T-1FF1136C Datasheet - Page 293
XC5VSX95T-1FF1136C
Manufacturer Part Number
XC5VSX95T-1FF1136C
Description
FPGA Virtex®-5 Family 94208 Cells 65nm (CMOS) Technology 1V 1136-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VSX95T-1FF1136C
Package
1136FCBGA
Family Name
Virtex®-5
Device Logic Units
94208
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
640
Ram Bits
8994816
Number Of Logic Elements/cells
94208
Number Of Labs/clbs
7360
Total Ram Bits
8994816
Number Of I /o
640
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1136-BBGA, FCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
Number Of Gates
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
SSTL18_II_T_DCI (1.8V) Split-Thevenin Termination
Table 6-35
Table 6-35: Differential SSTL (1.8V) Class II DC Voltage Specifications
Figure 6-86
SSTL18_II_T_DCI (1.8V) with on-chip split-Thevenin termination. In this bidirectional I/O
standard, when 3-stated, the termination is invoked on the receiver and not on the driver.
Because the Thevenin termination on the I/O is disabled for a driving I/O, the line is
equivalent to the SSTL18_I termination scheme. This allows the line to be driven by the
weaker SSTL class I driver. The SSTL18_II_T_DCI standard behaves like a normal
SSTL18_II I/O in a bidirectional environment but has the advantage of lower drive
strength and lower power consumption due to the optimized termination circuit.
Notes:
1. V
2. Per EIA/JESD8-6, “The value of V
3. V
4. V
5. V
V
Input Parameters
V
V
V
V
V
Output Parameters
V
CCO
TT
IN
ID
ID
IX
OX
the use conditions specified by the user.”
IN
ID
IX
OX
(AC)
(DC)
(DC)
(AC)
(AC)
(AC) indicates the voltage where the differential input signals must cross.
(DC) specifies the allowable DC excursion of each differential input.
(DC) specifies the input differential voltage required for switching.
(AC) indicates the voltage where the differential output signals must cross.
(4)
(1)
(3)
(5)
lists the differential SSTL (1.8V) Class II DC voltage specifications.
shows a sample circuit illustrating a valid termination technique for
www.xilinx.com
REF
is to be selected by the user to provide optimum noise margin in
Specific Guidelines for I/O Supported Standards
–0.30
0.675
0.725
Min
0.25
0.50
1.7
–
V
CCO
Typ
1.8
–
–
–
–
–
× 0.5
V
V
V
CCO
CCO
CCO
1.125
1.075
Max
1.9
–
+ 0.30
+ 0.60
+ 0.60
293
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