XC6VCX240T-1FFG1156C Xilinx Inc, XC6VCX240T-1FFG1156C Datasheet - Page 36

• Manufacturer Part Number: XC6VCX240T-1FFG1156C
• Description: FPGA Virtex®-6 CXT Family 241152 Cells 40nm (CMOS) Technology 1V 1156-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™ 6 CXTr

Specifications of XC6VCX240T-1FFG1156C

• Package: 1156FCBGA
• Family Name: Virtex®-6 CXT
• Device Logic Units: 241152
• Number Of Registers: 301440
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 600
• Ram Bits: 15335424
• Number Of Logic Elements/cells: 241152
• Number Of Labs/clbs: 18840
• Total Ram Bits: 15335424
• Number Of I /o: 600
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1156-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CLB Distributed RAM Switching Characteristics (SLICEM Only)
Table 48: CLB Distributed RAM Switching Characteristics
CLB Shift Register Switching Characteristics (SLICEM Only)
Table 49: CLB Shift Register Switching Characteristics
DS153 (v1.6) February 11, 2011
Product Specification
Notes:
1.
2.
Notes:
1.
Sequential Delays
T
T
Setup and Hold Times Before/After Clock CLK
T
T
T
T
Clock CLK
T
T
Sequential Delays
T
T
T
Setup and Hold Times Before/After Clock CLK
T
T
T
Clock CLK
T
AS
SHCKO
SHCKO_1
DS
WS
CECK
MPW
MCP
REG
REG_MUX
REG_M31
WS
CECK
DS
MPW
/T
/T
/T
A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case”, but if a “0” is
listed, there is no positive hold time.
T
A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case”, but if a “0” is
listed, there is no positive hold time.
/T
/T
AH
SHCKO
DH
DH
WH
/T
WH
/T
Symbol
Symbol
CKCE
CKCE
also represents the CLK to XMUX output. Refer to the TRACE report for the CLK to XMUX path.
Clock to A – B outputs
Clock to AMUX – BMUX outputs
A – D inputs to CLK
Address An inputs to clock
WE input to clock
CE input to CLK
Minimum pulse width
Minimum clock period
Clock to A – D outputs
Clock to AMUX – DMUX output
Clock to DMUX output via M31 output
WE input
CE input to CLK
A – D inputs to CLK
Minimum pulse width
Description
Description
www.xilinx.com
0.40/–0.01
0.41/–0.02
0.10/–0.02
0.09/–0.01
0.88/0.22
0.27/0.70
0.94/0.24
1.36
1.71
1.00
2.00
1.58
1.93
1.55
0.85
-2
-2
Virtex-6 CXT Family Data Sheet
Speed Grade
Speed Grade
0.48/–0.01
0.11/–0.01
1.01/0.26
0.31/0.80
0.46/0.00
0.10/0.00
1.08/0.28
1.56
1.96
1.15
2.30
1.82
2.22
1.78
0.98
-1
-1
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
Units
Units
36