MAX2769ETI+T Maxim Integrated Products, MAX2769ETI+T Datasheet - Page 14

• Manufacturer Part Number: MAX2769ETI+T
• Description: RF Receiver Low-Power GPS and GL ONASS Receiver with
• Manufacturer: Maxim Integrated Products

Specifications of MAX2769ETI+T

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ter. This selects between bit
and bit
ized, the data stream consists of bit
alization of bit
data pattern consists of 16 bits of bit
16 bits of bit
16 bits of bit
clock must be at least twice as fast as the ADC clock. If a
4-bit serialization of bit
serial clock must be at least four times faster than the
ADC clock.
The ADC data is loaded in parallel into four holding reg-
isters that correspond to four ADC outputs. Holding reg-
isters are 16 bits long and are clocked by the ADC clock.
Universal GPS Receiver
14
Figure 3. DSP Interface Top-Level Connectivity and Control Signals
______________________________________________________________________________________
0
, bit
REF/XTAL
PIN 15
1
1
, bit
0
0
(or bit
data, and so on. In this case, the serial
and bit
2
, and bit
2
) data, which, in turn, is followed by
0
1
, bit
REFDIV<1:0>
THROUGH
(or bit
x2
1
/2
/4
3
0
, bit
; bit
cases. If only bit
2
ADCCLK_SEL
SERCLK_SEL
2
) is selected, the stream
0
, and bit
and bit
0
data only. If a seri-
0
ADC
data followed by
3
1
; bit
is chosen, the
L_CNT<11:0>
M_CNT<11:0>
CLK_IN
FROM 3-WIRE
0
INTERFACE
0
CONTROL
SIGNALS
and bit
is serial-
Q
I
CLK_OUT
2
;
FRCLK_SEL
At the end of the 16-bit ADC cycle, the data is trans-
ferred into four shift registers and shifted serially to the
output during the next 16-bit ADC cycle. Shift registers
are clocked by a serial clock that must be chosen fast
enough so that all data is shifted out before the next set
of data is loaded from the ADC. An all-zero pattern fol-
lows the data after all valid ADC data are streamed to the
output. A DATASYNC signal is used to signal the begin-
ning of each valid 16-bit data slice. In addition, there is a
TIME_SYNC signal that is output every 128 to 16,384
cycles of the ADC clock.
CLK_ADC
STRM_EN
BIT 0
BIT 1
BIT 2
BIT 3
STRM_EN
STRM_START
STRM_STOP
STRM_COUNT<2:0>
DIEID<1:0>
STRM_BITS<1:0>
FRM_COUNT<27:0>
STAMP_EN
DAT_SYNCEN
TIME_SYNCEN
STRM_RST
DATA_SYNC
TIME_SYNC
DATA_OUT
CLK_SER
CLK_SER
STRM_EN
OUTPUT
DRIVER
PIN 21
PIN 20
PIN 17
PIN 18