ATA5811-PLQW Atmel, ATA5811-PLQW Datasheet
ATA5811-PLQW
Specifications of ATA5811-PLQW
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ATA5811-PLQW Summary of contents
Page 1
... Adjustable Output Power dBm Adjusted and Stabilized with External Resistor • ESD Protection at all Pins (2 kV HBM, 200 V MM) • Supply Voltage Range: 2.4V to 3.6V or 4.4V to 6.6V • Temperature Range: –40°C to +105°C • Small QFN48 Package UHF ASK/FSK Transceiver ATA5811 ATA5812 4689F–RKE–08/06 ...
Page 2
... The device supports data rates of 1 Kbit Kbit/s (FSK) and 1 Kbit Kbit/s (ASK) in Manchester, Bi-phase and other codes in transparent mode. The ATA5811 can be used in the 433 MHz to 435 MHz and the 868 MHz to 870 MHz band, the ATA5812 in the 314 MHz to 316 MHz band ...
Page 3
... System Block Diagram Antenna Matching Figure 1-2. 4689F–RKE–08/06 ATA5811/ATA5812 RF transceiver Digital control logic Microcontroller XTO Pinning QFN48 RF_IN 433_N868 6 ATA5811/ATA5812 NC 7 R_PWR 8 PWR_H 9 RF_OUT ATA5811/ATA5812 Power supply Microcontroller interface RSSI DEM_OUT 34 SCK 33 SDI_TMDI 32 SDO_TMDO 31 CLK 30 IRQ 29 N_RESET 28 VSINT XTAL2 ...
Page 4
... DEM_OUT RSSI 37 CDEM 38 RX_TX2 39 RX_TX1 40 PWR_ON 41 T5 ATA5811/ATA5812 4 Function Not connected Not connected Not connected RF input Not connected Selects RF input/output frequency range Not connected Resistor to adjust output power Pin to select output power RF output Not connected Not connected Not connected Not connected ...
Page 5
... FREQ frequency FREF synthesizer Signal processing (Mixer, IF Demod_Out filter, IF amplifier, demodulator, data filter data slicer) GND ATA5811/ATA5812 DVCC Digital control logic Power supply Switches regulators wakeup reset TX/RX - data buffer control register status register polling circuit bit check logic Reset XTO ...
Page 6
... Due to the single-ended and ground-referenced design, the loop antenna can be a free-form wire around the application usually employed in RKE uni-directional systems. The ATA5811/ATA5812 provides suffi- cient isolation and robust pulling behavior of internal circuits from the supply voltage as well as an integrated VCO inductor to allow this ...
Page 7
... are matching inductors of about 5 nH. A load capacitor for the crys typically 22 k and sets the output power at RF_OUT to about 1 1 ATA5811/ATA5812 C 6 CDEM RSSI CS DEM_OUT SCK SDI_TMDI Microcontroller SDO_TMDO ...
Page 8
... C used for the internal quasi peak detector and for the highpass frequency of the data filter are RF matching capacitors in the range pF 5 nH. L integrated. R ATA5811/ATA5812 RF_IN NC 5 433_N868 ATA5811/ATA5812 R_PWR PWR_H RF_OUT Lithium cells + shows a typical 433.92 MHz 2-battery RKE key fob or sensor application. The exter- ...
Page 9
... A lock detector within the synthesizer ensures that the transmission Figure 3-1 on page 7. = 133.5 kHz and f lo_IF 1. –120 dBC/Hz at ±1 MHz and –75 dBC at ±FREF at 433.92 MHz ATA5811/ATA5812 Table 6-1 on Figure 2-1 on page 6). The receiver can = 318.5 kHz). The demodulator needs a hi_IF ...
Page 10
... Z(RF_IN) 1278 //2.1 pF 925 //2.1 pF (21-j78) 311 //2 dB. Note that value 11. These measurements were done with Table 5-2, resulting in estimated matching losses / loss Table 5-3 Table 11-3 on page ATA5811/ATA5812 4 RF_IN 6 Figure 5-1 and with -3 are and Table 5 ...
Page 11
... Kbit/s 5.0 Kbit/s –117.5 dBm –115 dBm –116.5 dBm –114.0 dBm –113.0 dBm –111.5 dBm -40 - Frequency Offset (kHz) ATA5811/ATA5812 -3 BR_Range_2 10 Kbit/s –108.0 dBm –107.0 dBm –104.0 dBm -3 BR_Range_2 10 Kbit/s –113.5 dBm –112.5 dBm –109.5 dBm Figure 5-2 = –40°C, +25°C and +105°C and supply voltage ...
Page 12
... ATA5811/ATA5812 12 Figure 5-2 on page 11 For the demodulator used in the ATA5811/ATA5812, the tolerable frequency offset does not change with the data frequency, hence, the value of ±58 kHz is valid for Kbit/s. 33). Table 9-7 on page 36 and Table 9-10 on page ±2.5 ppm = ±128.66 ppm for 433.92 MHz and ± ...
Page 13
... Wide Band 3 dB Blocking Characteristic at 433.92 MHz 80,0 70,0 60,0 50,0 40,0 30,0 20,0 10,0 0,0 -10,0 -50,0 -40,0 -30,0 -20,0 Distance of Interfering to Receiving Signal [MHz] ATA5811/ATA5812 Figure 5-4 wide band blocking characteristics. The -1,0 0,0 1,0 2,0 3,0 4,0 5,0 -10,0 0,0 10,0 20,0 30,0 40,0 ...
Page 14
... Table 5-6. The ATA5811/ATA5812 can also receive FSK and ASK modulated signals if they are much higher than the I1dBCP. It can typically receive useful signals at 10 dBm. This is often referred to as the nonlinear dynamic range which is the maximum to minimum receiving signal which is 116 dB for 20 Kbit/s Manchester ...
Page 15
... IF filter. Hence the demodulator, data filter and data slicer are important in that case. The data filter of the ATA5811/ATA5812 implies a quasi peak detector. This results in a good suppression of the above mentioned disturbers and exhibits a good carrier to Gaussian noise performance ...
Page 16
... ETSI and CEPT regulations when using a simple LC filter for the power amplifier harmonics shown in ter of the FSK transmission and the power amplifier is switched on and off to perform the modulation. ulation with pseudo random data with 20 Kbit/s/±16.17 kHz/Manchester and 5 dBm output power. ATA5811/ATA5812 16 Typical RSSI Characteristic versus Temperature and Supply Voltage 1100 1000 900 ...
Page 17
... Figure 5-8. Unmodulated TX Spectrum f Ref 10 dBm Samp Log 10 dB/ VAvg Center 433.92 MHz Res BW 10 kHz 4689F–RKE–08/06 Atten 20 dB VBW 100 kHz FSK_L Atten 20 dB VBW 10 kHz ATA5811/ATA5812 Span 30 MHz Sweep 7.5 ms (401 pts) Span 1 MHz Sweep 27.5 ms (401 pts) 17 ...
Page 18
... There must be also a low resistive DC path to AVCC to deliver the DC current of the power amplifier's last stage. The matching of the PA output was done with the circuit according to ure 5-10 on page 19 elements may be necessary to compensate for individual board layouts. ATA5811/ATA5812 18 Atten 20 dB VBW 10 kHz ...
Page 19
... Characteristics: General” on page (10 nF) has to be placed close to the matching network 2 AVCC L RF OUT VPWR_H ATA5811/ATA5812 = 1.091 results in 9.1% less cur- 1 log(1.091) = 0.38 dB less output power 20. Looking to the 433.92 MHz/11 dBm case and the matching loss with L1 63 ATA5811/ATA5812 10 RF_OUT 8 R_PWR 1 9 PWR_H ...
Page 20
... Table 5- amb Table 5-9 on page 21 pared to 3.0V/25°C. As can be seen a temperature change to the power by less than 1 dB due to the bandgap regulated output current. Measurements of all the cases in same relative behavior as shown in ATA5811/ATA5812 20 0.4 56 5.7 27 10.5 27 0.1 56 6.2 ...
Page 21
... Z(RX_TX1) TX Mode MHz 315 (4.8 + j3.2) MHz 433.92 (4.5 + j4.3) MHz 868 j9) 2 ATA5811/ATA5812 3.0V –0 –0.8 dB Table 5-11 on page 22 should be used, but the exact Figure 5-11 on page 21 shows an approximate Figure 3-1 on page 7 Z(RX_TX1) RX Mode (11.3 – j214) (10.3 – j153) (8.9 – ...
Page 22
... RX mode hence the antenna bandwidth is higher than in TX mode. Table 5-11. Note that if matching like in Q > 70 should be used for L dominant. The RX and TX losses will be in the range of 1.0 dB there. ATA5811/ATA5812 22 has an impedance of about and C ...
Page 23
... XTAL with Load Capacitance XTAL fF, C 1.5 pF and fF, C 1.5 pF Lmin ATA5811/ATA5812 = 7.4 pF and C = 10.6 pF. The XTO oscil- Lmin Lmax 36). The remaining local oscillator tolerance at nominal is calculated using the following formula: XTAL the nominal load capacitance of the XTAL LN Crystal equivalent circuit ...
Page 24
... CLK_ON in control register 3 is High (see tions of the VSOUT and DVCC voltage also have to be fulfilled (see Figure 7-1 on page To save current in Idle and sleep mode, the load capacitors partially are switched off in this modes with S1 and S2 seen recommended to use a crystal with 1 2.2 pF. 0 ATA5811/ATA5812 ...
Page 25
... RF CREG1 Bit( (MHz) f XTO RF 0 13.25311 XTO 0 13.41191 XTO 1 12.73193 XTO ATA5811/ATA5812 CLK & DVCC_OK (from power supply) /3 CLK_ON VSOUT_OK (control (from power supply) register 3) XTO_OK (to reset logic) f DCLK / XDCLK /4 /8 /16 XLim Table 9-7 on page 36 and the f ...
Page 26
... The complete timing of the digital circuitry is derived from one clock. According to on page a divider DCLK T controls the following application relevant parameters: DCLK • Timing of the polling circuit including Bit-check • TX bit rate ATA5811/ATA5812 26 and f can cause interference with the received signals (FREQ_min = 3803, XTO CLK f XTO ---------- - 3 = 2.38V (typically ...
Page 27
... V_REG1 3.25V typ. EN FF1 SW_VSOUT change and P_On_Aux (Status register) OUT EN ATA5811/ATA5812 Table 9-20 on page 39) and XLim which 37). This clock cycle T XDCLK = 8 T XLim XDCLK DCLK = 4 T XLim XDCLK DCLK = 2 T XLim XDCLK DCLK = 1 T XLim XDCLK DCLK SW_AVCC AVCC DVCC ...
Page 28
... The supply voltage range of the ATA5811/ATA5812 is 2.4V to 3.6V or 4.4V to 6.6V. Pin VS1 is the supply voltage input for the range 2.4V to 3.6V and is used in battery applications using a single lithium 3V cell. Pin VS2 is the voltage input for the range 4.4V to 6.6V (2 Battery Application and Car Applications) in this case the voltage regulator V_REG1 regulates VS1 to typically 3. the voltage regulator is active a blocking capacitor of 2.2 µ ...
Page 29
... VSOUT_EN = 0 Event on Pin T1, T2, T3 Polling Mode AVCC = VS1 DVCC = VS1 VSOUT = OFF < 3.5V (typically) the transceiver is in OFF mode. In OFF mode AVCC, DVCC and VAUX ATA5811/ATA5812 V < 3.5V (typ) VAUX V > 3.5V (typ) VAUX Pin PWR_ON = 1 or Pin T1, T2, T3 Pin T5 or ...
Page 30
... XTO has elapsed (amplitude detector, see Figure 6-2 on page time of the XTO has elapsed the output clock at pin CLK is available. Because the enabling of pin CLK is asynchronous the first clock cycle may be incomplete. ATA5811/ATA5812 30 < VS1 + 0.5V, VSOUT is connected to VS1 for the appropriate application case. ...
Page 31
... V > 2.38V and the XTO is running SOUT V > 2.3V and the XTO is running SOUT ATA5811/ATA5812 drops below V VSOUT exceeds V and the status register is read via Thres_2 was prior disabled by the VSOUT ...
Page 32
... The supply voltage range is 2.4V to 3.6V and VAUX is not used. Figure 7-5. ATA5811/ATA5812 32 Reset Logic, SR Latch Generates the Hysteresis in the NRESET Signal DVCC_OK and XTO_OK VSOUT_EN and VSOUT_OK LOW_BATT 1-Battery Application ATA5811/ATA5812 VS1 VS2 VAUX RF-Transceiver AVCC Digital Control DVCC Logic VSOUT VSINT CS SCK ...
Page 33
... Figure 4-1 on page connect the microcontroller and the pin VSINT directly 8-bit control register and is write and readable via a 4-wire serial 8-bit status register is not part of the RAM and is readable via the 4-wire serial interface. ATA5811/ATA5812 Microcontroller 4.4V to 6.6V VS OUT ...
Page 34
... VS1 or DVCC = V_REG2) and gets lost if the transceiver is in OFF mode (DVCC = OFF). After the transceiver is turned on via pin PWR_ON = High Low Low Low Low Low or the voltage at pin VAUX V are in the default state. Figure 9-1. ATA5811/ATA5812 34 Register Structure MSB AVCC_ OPM 1 ...
Page 35
... Pin IRQ is set bytes still are in the TX/RX data buffer or the TX data buffer is empty 0 (default) 1 Pin IRQ is set the TX data buffer is empty Control Register 1 (Function of Bit 5) Function 0 (default) 1 Enables AVCC, if the ATA5811/ Control Register 1 (Function of Bit 4) Function 0 433/868 MHz 1 315 MHz Control Register 1 (Function of Bit 2 and Bit 1) OPM0 Function ...
Page 36
... Control Register 3 (ADR 2) Table 9-10. FR8 Note: ATA5811/ATA5812 36 Control Register 1 (Function of Bit 0) Function 0 TX and RX function via TX/RX data buffer (default) Transparent mode, TX/RX data buffer disabled, TX modulation data stream via pin 1 SDI_TMDI, RX modulation data stream via pin SDO_TMDO Control Register 2 (Function of Bit 7, Bit 6, Bit 5, Bit 4, Bit 3, Bit 2 and Bit 1) ...
Page 37
... Control Register 4 (Function of Bit 1) Function extended T off (default) Sleep Sleep extended T on Sleep Sleep Control Register 4 (Function of Bit 0) Function extended TLim_min, TLim_max off (default) Lim extended Lim Lim_min ATA5811/ATA5812 Function Sleep (T = Sleep 1024 T Sleep DCLK 1024 T Sleep DCLK (default Lim_max X ) Sleep X ) ...
Page 38
... Control Register 5 (Function of Bit 5, Bit 4, Bit 3, Bit 2, Bit 1 and Bit Mode) Lim_min5 Lim_min4 Lim_min3 ATA5811/ATA5812 38 Control Register 5 (Function of Bit 7 and Bit 6) BitChk0 Function bits checked during Bit-check) Bit-check bits checked during Bit-check (default)) Bit-check bits checked during Bit-check) Bit-check bits checked during Bit-check) Bit-check Lim_min2 ...
Page 39
... Bit-rate range 3 (B3) 8.0 Kbit/s to 20.0 Kbit/ XDCLK DCLK Note that the receiver is not working with >10 Kbit/s in ASK mode Lim_max2 Lim_max1 Lim_max0 ATA5811/ATA5812 X Lim X Lim X ; (default) Lim X , Lim Function Lim_max (Lim_max < 12 Are Not Applicable (Lim_max – 1) Lim_max (28 – Lim_max (default XDCLK ) ...
Page 40
... Status Register (ADR 8) Table 9-22. Status Bit ST5 ST4 ST3 ST2 ST1 Power_On Low_Batt P_On_Aux ATA5811/ATA5812 40 Status Register Function Status of pin T5 Pin ST5 = 1 Pin ST5 = 0 (see Figure 9-3 on page 42) Status of pin T4 Pin ST4 = 1 Pin ST4 = 0 (see Figure 9-3 on page 42) ...
Page 41
... Figure 9-2). The transceiver recognize the negative edge, sets pin Tn_IRQ exceeds 1.5V (typically) and the XTO is settled, the digital control logic is active and = 2.38V (typ 2.3V (typ) Thres_1 T Tn_IRQ IDLE Mode ATA5811/ATA5812 V ). Tn_IRQ exceeds 2.38V VSOUT ) for VS2 41 ...
Page 42
... While the debounce counter is running, the bits VSOUT_EN and CLK_ON in control register 3 are set to 1. The interrupt is deleted after reading the status register or executes the command Delete_IRQ pin Tn is not used, it can be left open because of an internal pull-up resistor (typically Figure 9-3. ATA5811/ATA5812 DCLK ...
Page 43
... It is not possible to set the transceiver to OFF mode by setting pin PWR_ON pin PWR_ON is not used, it must be connected to GND. T > PWR_ON PWR_ON_IRQ_1 = 2.38V (typ 2.3V Thres_1 (typ) T PWR_ON_IRQ_1 IDLE Mode ATA5811/ATA5812 ). PWR_ON_IRQ_1 VSOUT ). The state transition Power_On 0 > T PWR_ON PWR_ON_IRQ_2 T PWR_ON_IRQ_2 IDLE, AUX, RX, RX Polling, TX Mode exceeds 2. gen- 43 ...
Page 44
... Low Battery Indicator The status bit Low_Batt is set the voltage on pin VSOUT V (typically). Low_Batt is set interface (see Figure 9-5. ATA5811/ATA5812 44 exceeds V and the status register is read via the 4-wire serial VSOUT Thres_2 Figure 7-3 on page 31). Timing Status Bit Low_Batt IDLE, AUX, TX, RX ...
Page 45
... P_On_Aux is set to 1 and an interrupt is issued. > VS1 + 0.5V sets P_On_Aux to 1. The state transition P_On_Aux 0 V VAUX = 2.38V (typ) = 2.3V (typ) AUX Mode ATA5811/ATA5812 exceeds 2V (typically) pin N_RESET is set to low, VSOUT > VS1 + 0.5V (typ) V > VS1 + 0.5V (typ) VAUX IDLE, TX, RX, RX polling ...
Page 46
... TX data bytes are provided for the microcontroller on pin SDO_TMDO. Figure 10-2. Write TX/RX Data Buffer MSB SDI_TMDI Command: Write TX/RX Data Buffer SDO_TMDO Nr. Bytes in the TX/RX Data Buffer SCK CS ATA5811/ATA5812 46 LSB MSB LSB MSB X RX Data Byte 1 LSB MSB ...
Page 47
... Command: Read C/S Register Z Data C/S Register X LSB MSB LSB MSB Data Control Register X Command: Write Control Register Y Write Control Register X MSB SDI_TMDI Command: OFF Command SDO_TMDO Nr. Bytes in the TX/RX Data Buffer SCK CS ATA5811/ATA5812 LSB Data C/S Register Y LSB Data Control Register X LSB 47 ...
Page 48
... Data Input (SDI_TMDI) and the Serial Data Output (SDO_TMDO). Data is transmitted/received bit by bit in synchronization with the serial clock. Note: When CS is low and the transparent mode is inactive (T_MODE = 0), SDO_TMDO high-impedance state. When CS is low and the transparent mode is active (T_MODE = 1), the RX data stream is available on pin SDO_TMDO. ATA5811/ATA5812 48 SDI_TMDI SDO_TMDO SCK CS ...
Page 49
... This transfer take place either via the TX/RX data buffer or via the pin SDO_TMDO. 4689F–RKE–08/06 T CS_setup Cycle T Hold Setup MSB X MSB-1 T Out_enable Out_delay MSB Control Register 1 OPM1 OPM0 1 1 ATA5811/ATA5812 T CS_disable T SCK_setup2 Out_disable MSB-1 LSB Function 0 RX polling mode 1 RX mode T SCK_hold X 49 ...
Page 50
... The sleep time can be extended to about 300 ms by setting X (which is done by setting XSleep in control register 4 to 1), the time resolution is then about 9.6 ms. 11.1.3 Start-up Mode During T circuit starts up (T ready to receive. ATA5811/ATA5812 50 . During the start-up period, T IDLE_X Bit-check the current consumption ...
Page 51
... Set VSOUT_EN = 1 NO Set CLK_ON = 1 Set OPM0 = 1 NO P_MODE = 0 ? YES Set IRQ NO Start bit detected ? YES Data Buffer NO Bit error ? ATA5811/ATA5812 Sleep: Defined by bits Sleep 0 to Sleep 4 in Control Register Defined by bit XSleep in Control register 4 Sleep Basic clock cycle T : DCLK T : 798.5 T ...
Page 52
... SLEEP ? YES Receiving mode: The incomming data stream is passed via PIN SDO_TMDO to the connected microcontroller bit error occurs the transceiver is not set back to Start-up mode. Output level on pin RX_ACTIVE High RX_X RX data stream available on pin ATA5811/ATA5812 IDLE_X High Startup_PLL_X Startup_PLL High ...
Page 53
... Bit-check is defined by two separate time lim between the lower Bit-check limit the check will be continued Lim_max , the Bit-check will be terminated and the transceiver switches to sleep mode. Demod_Out ATA5811/ATA5812 Bit-check Bit-check 1/2 Bit 1/2 Bit 1/2 Bit Receiving mode ...
Page 54
... CV_Lim reaches Lim_max. This is illustrated in Figure 11-5. Timing Diagram During Bit-check (Lim_min = 14, Lim_max = 24) RX_ACTIVE Bit check Demod_Out Bit-check counter 0 T Startup_Sig_Proc Start-up mode ATA5811/ATA5812 time window of ±38%, to get the maximum sensitivity the ee = Lim_min T XDCLK = (Lim_max – XDCLK , T and T ...
Page 55
... Bit_check Bit check mode is given in the electrical characteristics. T Bit-check XDCLK resulting in a lower current consumption in RX polling mode. , and the count of the bits, N Bit-check requiring a higher value for the transmitter preburst T Bit-check ATA5811/ATA5812 0 T Sleep Sleep mode Lim_max Sleep Sleep mode varies for each check ...
Page 56
... T Lim_min_2T Upper limit of 2T: Lim_max_2T T Lim_max_2T If the result of Lim_min_2T or Lim_max_2T is not an integer value, it will be round up. ATA5811/ATA5812 56 '0' '1' '0' '0' '0' '0' '0' '1' '1' '1' '1' '0' '0' '1' '1' '0' '1' '0' '1' '1' '0' '0' Receiving mode Figure 11-9 on page 57, only two distances between two edges in Manchester and Bi-phase ...
Page 57
... Lim_min b) Logical error (no edge detected in the bit center) The byte consisting of the bit error will not be stored in the TX/RX data buffer. Thus it is not avail- able via the 4-wire serial interface. ATA5811/ATA5812 Byte 16, Byte 32, ... Byte 15, Byte 31, ... Byte 14, Byte 30, ... Byte 13, Byte 29, ... ...
Page 58
... RF XTAL MHz BR_Range_0/XLim = 1 315.0 Lim_min = 13 (261 µs) (12.73193) Lim_max = 38 (744 µs) 433.92 Lim_min = 13 (251 µs) (13.25311) Lim_max = 38 (715 µs) 868.3 Lim_min = 13 (248 µs) (13.41191) Lim_max = 38 (706 µs) ATA5811/ATA5812 58 Start-up mode Bit-check mode RX Modulation Scheme ASK/_NFSK T_MODE have been done with the Lim_min and Lim_max values according to 2 ...
Page 59
... The modulation is selected with ASK_/NFSK in control 46 byte is loaded, the counter is incremented byte is transmit- Writing to the control register during TX mode, resets the TX/RX data buffer and the counter which indicates the number of bytes to be transmitted. illustrates the flow chart of the TX transparent mode. ATA5811/ATA5812 OPM0 Function 1 TX mode 60 ...
Page 60
... Figure 11-11. TX Operation (T_MODE = 0) Command: Delete_IRQ N Pin IRQ = Write Control Register 1 OPM1, OPM0: Set IDLE ATA5811/ATA5812 60 Write Control Register 6 Baud1, BAUD0: Select baud rate range Lim_max0 to Lim_max5: Don't care Write Control Register 5 Lim_min0 to Lim_min5: Select the baud rate Bit_ck0, Bit_ck1: Don't care ...
Page 61
... Adjust f RF Set VSOUT_EN = 1 Don't care Adjust f RF Don't care Don't care Don't care Select operation frequency Set OPM1 = 0 and OPM0 = 1 Set T_mode = 1 Apply TX Data on Pin SDI_TMDI Set IDLE (OPM1 = 0, OPM0 = 1 ATA5811/ATA5812 Idle Mode Start-up Mode (TX 331.5 T Startup DCLK TX Mode Idle Mode 61 ...
Page 62
... Bytes are in the TX data buffer or the TX data buffer is empty (depends on IR0 and IR1 in control register 1). Events During RX Operation (T_MODE = received bytes are in the RX data buffer or a receiving error is occurred (depends on IR0 and IR1 in control register 1). Successful Bit-check (P_MODE = 0) Note: ATA5811/ATA5812 62 Bit in TX/RX P_Mode T_Mode Data Buffer ...
Page 63
... Pin Symbol AVCC VS2 = battery) I S_OFF = VAUX = 0 V (car) Table 5-2 on page 10 and RF_OUT matched to 50 Table 5-7 on page 20. ATA5811/ATA5812 Min. Max. 150 –55 +125 –40 +105 –0.3 +7.2 –0.3 +4 –0.3 +7.2 –0.3 +5.5 –2 +2 –200 +200 10 Value 2.4V to 3.6V (1-battery application), V ...
Page 64
... Bit rate 2.4 Kbit/s *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note: 1. Pin numbers in brackets mean they were measured with RF_IN matched to 50 component values according to with component values according to ATA5811/ATA5812 64 = –40°C to +105°C, V amb VS1 = ...
Page 65
... REF1 REF2 + P + REF_FSK REF1 REF2 ( ±22 kHz, 6 kHz = ±16 kHz hence ±52 kHz Table 5-2 on page 10 and RF_OUT matched to 50 Table 5-7 on page 20. ATA5811/ATA5812 = V = 2.4V to 3.6V (1-battery application), V VS2 VS1 Min. Typ. Max. –110.5 –112.5 –114.0 –114.5 –116.5 –118.0 –1.0 REF1 +2.7 – ...
Page 66
... Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note: 1. Pin numbers in brackets mean they were measured with RF_IN matched to 50 component values according to with component values according to ATA5811/ATA5812 66 = –40°C to +105°C, V amb VS1 = V = 4.75V to 5.25V (car application). Typical values are given at V ...
Page 67
... P RFIN_Low = 433.92 MHz = 868.3 MHz = 315 MHz (4 RFIN_High = 433.92 MHz = 868.3 MHz (4 Table 5-2 on page 10 and RF_OUT matched to 50 Table 5-7 on page 20. ATA5811/ATA5812 = V = 2.4V to 3.6V (1-battery application), V VS2 VS1 Min. Typ. Max. 2 FSK0-2 4 FSK3 10 ASK 70 RSSI –116 –115 –112.3 –46 – ...
Page 68
... RF *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note: 1. Pin numbers in brackets mean they were measured with RF_IN matched to 50 component values according to with component values according to ATA5811/ATA5812 68 = –40°C to +105°C, V amb VS1 = V = 4.75V to 5.25V (car application). Typical values are given at V ...
Page 69
... MHz = 1 433.92 MHz = 27 k (10 1 868.3 MHz = 0 1 Table 5-2 on page 10 and RF_OUT matched to 50 Table 5-7 on page 20. ATA5811/ATA5812 = V = 2.4V to 3.6V (1-battery application), V VS2 VS1 Min. Typ. Max. –2.5 0 +2.5 REF1 8.5 8.6 9.6 3.5 5.0 REF2 according to Figure 5-1 on page 10 ...
Page 70
... VS1 *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note: 1. Pin numbers in brackets mean they were measured with RF_IN matched to 50 component values according to with component values according to ATA5811/ATA5812 70 = –40°C to +105°C, V amb VS1 = V = 4.75V to 5.25V (car application). Typical values are given at V ...
Page 71
... C and 7.0 fF 120 Table 5-2 on page 10 and RF_OUT matched to 50 Table 5-7 on page 20. ATA5811/ATA5812 = V = 2.4V to 3.6V (1-battery application), V VS2 VS1 Min. Typ. Max. (36 – j502) (19 – j366) (2.8 – j141) –125 –126 –127 XTO1 –50 f XTAL –100 +100 ...
Page 72
... TX mode) *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note: 1. Pin numbers in brackets mean they were measured with RF_IN matched to 50 component values according to with component values according to ATA5811/ATA5812 72 = –40°C to +105°C, V amb VS1 = V = 4.75V to 5.25V (car application). Typical values are given at V ...
Page 73
... Loop_PLL = 315 MHz = 433.92 MHz f DEV_TX = 868.3 MHz = 315 MHz = 433.92 MHz Step_PLL = 868.3 MHz Table 5-2 on page 10 and RF_OUT matched to 50 Table 5-7 on page 20. ATA5811/ATA5812 = V = 2.4V to 3.6V (1-battery application), V VS2 VS1 Min. Typ. Max. –72 TX –68 –70 –70 TX –66 –60 < ...
Page 74
... V *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note: 1. Pin numbers in brackets mean they were measured with RF_IN matched to 50 component values according to with component values according to ATA5811/ATA5812 74 = –40°C to +105°C, V amb VS1 = V = 4.75V to 5.25V (car application). Typical values are given at V ...
Page 75
... VSINT = Load capacitance 30, 27 CCLK I VSINT VSINT I I VSOUT EXT I I VSINT VSINT EXT VSOUT Table 5-2 on page 10 and RF_OUT matched to 50 Table 5-7 on page 20. ATA5811/ATA5812 = V = 2.4V to 3.6V (1-battery application), V VS2 VS1 Min. Typ. Max CLK --------------------------------------------------------------------------- - VSINT 3 < 10 µA < 10 µ ...
Page 76
... TX PWR_H = AVCC mode) *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note: 1. The voltage of VAUX may rise up to 2V. The current I ATA5811/ATA5812 76 = –40°C to +105°C, V amb VS1 = V = 4.75V to 5.25V (car application). Typical values are given at V ...
Page 77
... V 3V VS1 VS2 17 RX_VS1 17, 18, enabled VSOUT 22 VS1 VS2 17 Startup_PLL_VS1 may not exceed 100 µA. VAUX ATA5811/ATA5812 = V = 2.4V to 3.6V typical values at V VS2 Min. Typ. Max. 2.4 V VSOUT VS1 V 2.4 5.25 VSINT 100 Thres 2.18 2.3 2.42 Thres_1 2.26 2.38 2.5 ...
Page 78
... TX mode CLK disabled V *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note: 1. The voltage of VAUX may rise up to 2V. The current I ATA5811/ATA5812 78 = –40°C to +105°C, V amb VS1 Figure 2-1 on page 315.0 MHz/433.92 MHz/868.3 MHz unless otherwise specified ...
Page 79
... VSINT 6V VS2 = 0 enabled VSOUT 17 I IDLE_VS2 enabled VSOUT disabled VSOUT 17 may not exceed 100 µA. VAUX ATA5811/ATA5812 = 4.4V to 6.6V typical values at V VS2 Min. Typ. Max. VS2 I or IDLE_VS2 I or RX_VS2 I or Startup_PLL_VS2 I TX_VS2 V 4.4 6.6 VS2 3.0 3 ...
Page 80
... Supply current V 10.16 TX mode CLK disabled V *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note: 1. The voltage of VAUX may rise The current I ATA5811/ATA5812 80 = –40°C to +105°C, V amb VS2 315.0 MHz/433.92 MHz/868.3 MHz unless otherwise specified RF Pin Symbol ...
Page 81
... Thres_1 enabled VSOUT 17 IDLE_VS2_VAUX enabled VSOUT disabled VSOUT 17, 19 RX_VS2_VAUX 17, VSOUT 19, 22, 27 ATA5811/ATA5812 = 4.75V to 5.25V. Typical values at V VS2 Min. Typ. Max. VAUX I VS2 IDLE_VS2,VAUX or I RX_VS2,VAUX or I Startup_PLL_VS2,VAUX or I TX_VS2,VAUX , V 4.75 5.25 AUX 3.0 3.5 VSOUT 2.4 5.25 VSINT V ...
Page 82
... MHz/5dBm 433.92 MHz/10dBm 868.3 MHz/10dBm CLK enabled Supply current in V 11.15 TX mode CLK disabled V *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter ATA5811/ATA5812 82 = –40°C to +105°C, V amb VS2 315.0 MHz/433.92 MHz/868.3 MHz unless otherwise specified RF Pin Symbol I ...
Page 83
... V amb VS1 = 4.75V to 5.25V (car application), typical values at V Pin Symbol T T XDCLK T T Startup_PLL T Startup_Sig_Proc = 1/( Bit_check Sig = ATA5811/ATA5812 = V = 2.4V to 3.6V (1-battery application and T VS1 VS2 amb Min. Typ. Max. 16/f 16/f DCLK XTO XTO DCLK ...
Page 84
... CS 15.8 CS disable time period Time period SCK low to 15.9 CS high *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter ATA5811/ATA5812 84 = –40°C to +105°C. V amb VS1 = 4.75V to 5.25V (car application), typical values at V Pin Symbol ...
Page 85
... 29 PWR_ON_IRQ_1 = 2.2 µ 2.2 µ 10nF ATA5811/ATA5812 = V = 2.4V to 3.6V (1-battery application and T VS1 VS2 amb Min. Typ. Max. 250 250 0.3 0.8 0.45 1.3 0.45 1.3 = 4.4V to VS2 = 25°C unless Unit Type ...
Page 86
... Push button debounce Every mode except 16.4 time OFF mode *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter ATA5811/ATA5812 86 = –40°C to +105°C. V amb VS1 = 4.75V to 5.25V (car application), typical values at V Pin Symbol 29 PWR_ON_IRQ_2 Figure 2-1 6, Figure 3-1 ...
Page 87
... Pin Symbol = 2.4V to 5.25V 2.4V to 5.25V 2.4V to 5.25V 2.4V to 5.25V 2.4V to 5.25V 2.4V to 5.25V 41, 42, 43, 44 41, 42, 43, 44 ATA5811/ATA5812 = 2.4V to 3.6V (1 Battery Application) and and T VS1 VS2 Min. Typ. Max. 0 VSINT 0 VSINT V VSINT 0 VSINT 0 VSINT V VSINT 0 VSINT 0 VSINT V VSINT 0.4 Il 0.8 ...
Page 88
... Saturation voltage low I DEM_OUT *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note logic high level is applied to this pin a minimum serial impedance of 100 temperature range. ATA5811/ATA5812 88 = –40°C to +105° amb VS1 S2 = 4.75V to 5.25V (Car Application) typical values at V ...
Page 89
... Ordering Information Extended Type Number ATA5811-PLQW ATA5812-PLQW 21. Package Information Package: QFN Exposed pad 5.1 x 5.1 Dimensions in mm Not indicated tolerances ± 0. Drawing-No.: 6.543-5089.02-4 Issue: 1; 14.01.03 4689F–RKE–08/06 Package Remarks QFN48 7 mm QFN48 max. +0 0.05 -0. ATA5811/ATA5812 7 mm, Pb-free 7 mm, Pb-free 7 5.5 5 ...
Page 90
... Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. 4689F-RKE-08/06 4689E-RKE-06/06 4689D-RKE-09/05 ATA5811/ATA5812 90 History Quality of drawings improved Put datasheet in a new template kBaud replaced through Kbit/s Baud replaced through bit Table 11-6 “ ...
Page 91
... Thermal Resistance ............................................................................... 63 14 Electrical Characteristics: General ...................................................... 63 15 Electrical Characteristic: 1-Battery Application .................................. 76 16 Electrical Characteristics: 2-Battery Application ................................ 79 17 Electrical Characteristics: Car Application ......................................... 81 18 Digital Timing Characteristics .............................................................. 83 19 Digital Port Characteristics ................................................................... 87 20 Ordering Information ............................................................................. 89 21 Package Information ............................................................................. 89 22 Revision History ..................................................................................... 90 4689F–RKE–08/06 ATA5811/ATA5812 91 ...
Page 92
... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...