72V265LA15TF Integrated Device Technology (Idt), 72V265LA15TF Datasheet
72V265LA15TF
Specifications of 72V265LA15TF
Related parts for 72V265LA15TF
72V265LA15TF Summary of contents
Page 1
FEATURES: • • • • • Choose among the following memory organizations: IDT72V255LA 8,192 x 18 IDT72V265LA 16,384 x 18 • • • • • Pin-compatible with the IDT72V275/72V285 and IDT72V295/ 72V2105 SuperSync FIFOs • • • • • Functionally ...
Page 2
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™ 8,192 x 18, 16,384 x 18 DESCRIPTION (CONTINUED) • • • • • The period required by the retransmit operation is now fixed and short. • • • • • The first word data ...
Page 3
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™ 8,192 x 18, 16,384 x 18 DESCRIPTION (CONTINUED) There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through (FWFT) mode. In IDT Standard mode, the ...
Page 4
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™ 8,192 x 18, 16,384 x 18 PIN DESCRIPTION Symbol Name D –D Data Inputs 0 17 MRS Master Reset PRS Partial Reset RT Retransmit FWFT/SI First Word Fall Through/Serial In WCLK Write Clock WEN ...
Page 5
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™ 8,192 x 18, 16,384 x 18 ABSOLUTE MAXIMUM RATINGS Symbol Rating V Terminal Voltage TERM with respect to GND T Storage STG Temperature I DC Output Current OUT NOTE: 1. Stresses greater than those ...
Page 6
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™ 8,192 x 18, 16,384 ELECTRICAL CHARACTERISTICS (Commercial 3.3V ± 0.3V 0°C to +70°C; Industrial Symbol Parameter f Clock Cycle Frequency S t Data Access ...
Page 7
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™ 8,192 x 18, 16,384 x 18 FUNCTIONAL DESCRIPTION TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH (FWFT) MODE The IDT72V255LA/72V265LA support two different timing modes of operation: IDT Standard mode or First Word ...
Page 8
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™ 8,192 x 18, 16,384 x 18 PROGRAMMING FLAG OFFSETS Full and Empty Flag offset values are user programmable. The IDT72V255LA/72V265LA has internal registers for these offsets. Default settings are stated in the footnotes of ...
Page 9
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™ 8,192 x 18, 16,384 x 18 IDT72V255LA ⎯ 8,192 BIT 17 12 EMPTY OFFSET REGISTER DEFAULT VALUE 07FH LOW at Master Reset, 3FFH HIGH at ...
Page 10
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™ 8,192 x 18, 16,384 x 18 SERIAL PROGRAMMING MODE If Serial Programming mode has been selected, as described above, then programming of PAE and PAF values can be achieved by using a combi- nation ...
Page 11
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™ 8,192 x 18, 16,384 FWFT mode is selected, the FIFO will mark the beginning of the Retransmit setup by setting OR HIGH. During this period, the internal read pointer is set ...
Page 12
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™ 8,192 x 18, 16,384 x 18 SIGNAL DESCRIPTION INPUTS: DATA IN (D0 - D17) Data inputs for 18-bit wide data. CONTROLS: MASTER RESET (MRS) A Master Reset is accomplished whenever the MRS input is ...
Page 13
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™ 8,192 x 18, 16,384 x 18 WRITE ENABLE (WEN) When the WEN input is LOW, data may be loaded into the FIFO RAM array on the rising edge of every WCLK cycle if the ...
Page 14
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™ 8,192 x 18, 16,384 x 18 EMPTY FLAG (EF/OR) This is a dual purpose pin. In the IDT Standard mode, the Empty Flag (EF) function is selected. When the FIFO is empty, EF will ...
Page 15
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™ 8,192 x 18, 16,384 x 18 MRS REN WEN t FWFT FWFT/ SEN EF/OR FF/IR PAE PAF RSS t RSS t RSS t ...
Page 16
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™ 8,192 x 18, 16,384 x 18 PRS REN WEN RT SEN EF/OR FF/IR PAE PAF RSS t RSS t RSS t RSS t RSF t ...
Page 17
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™ 8,192 x 18, 16,384 WRITE WCLK 1 (1) t SKEW1 WEN RCLK t t ENS ENH REN DATA IN ...
Page 18
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™ 8,192 x 18, 16,384 x 18 COMMERCIAL AND INDUSTRIAL 18 TEMPERATURE RANGES OCTOBER 22, 2008 ...
Page 19
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™ 8,192 x 18, 16,384 x 18 COMMERCIAL AND INDUSTRIAL 19 TEMPERATURE RANGES OCTOBER 22, 2008 ...
Page 20
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™ 8,192 x 18, 16,384 x 18 RCLK t t ENS ENH t RTS REN WCLK WEN t ENS RT EF PAE HF PAF NOTES: 1. ...
Page 21
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™ 8,192 x 18, 16,384 x 18 RCLK t t ENH ENS t RTS REN WCLK t RTS WEN t ENS RT OR PAE HF PAF NOTES: 1. ...
Page 22
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™ 8,192 x 18, 16,384 x 18 WCLK LD WEN Figure 14. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes) RCLK LD REN ...
Page 23
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™ 8,192 x 18, 16,384 CLKH t CLKL WCLK t t ENH ENS WEN (2) n words in FIFO PAE , (3) n+1 words in FIFO t (4) SKEW2 RCLK 1 REN ...
Page 24
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™ 8,192 x 18, 16,384 x 18 OPTIONAL CONFIGURATIONS WIDTH EXPANSION CONFIGURATION Word width may be increased simply by connecting together the control signals of multiple devices. Status flags can be detected from any one ...
Page 25
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™ 8,192 x 18, 16,384 x 18 DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY) The IDT72V255LA can easily be adapted to applications requiring depths greater than 8,192 and 16,384 for the IDT72V265LA with an 18-bit bus ...
Page 26
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™ 8,192 x 18, 16,384 x 18 ORDERING INFORMATION XXXXX X XX Device Type Power Speed NOTES: 1. Industrial temperature range product for 15ns speed grade is available as a standard device. All other speed ...
Page 27
VOLT CMOS SuperSync FIFO 8,192 x 18 16,384 x 18 DIFFERENCES BETWEEN THE IDT72V255LA/72V265LA AND IDT72V255L/72V265L IDT has improved the performance of the IDT72V255/72V265 SuperSync™ FIFOs. The new versions are designated by the “LA” mark. The LA part is ...