72V265LA15TF Integrated Device Technology (Idt), 72V265LA15TF Datasheet - Page 23

• Manufacturer Part Number: 72V265LA15TF
• Description: FIFO Mem Sync Dual Depth/Width Uni-Dir 16K x 18 64-Pin STQFP
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72V265LA15TF

• Package: 64STQFP
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 288 Kb
• Organization: 16Kx18
• Data Bus Width: 18 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 3.3 V
• Operating Temperature: 0 to 70 °C

NOTES:
1. n = PAE offset.
2. For IDT Standard mode
3. For FWFT mode.
4. t
5. PAE is asserted and updated on the rising edge of WCLK only.
NOTES:
1. For IDT Standard mode: D = maximum FIFO depth. D = 8,192 for the IDT72V255LA and 16,384 for the IDT72V265LA.
2. For FWFT mode: D = maximum FIFO depth. D = 8,193 for the IDT72V255LA and 16,385 for the IDT72V265LA.
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™
WCLK
WCLK
RCLK
8,192 x 18, 16,384 x 18
RCLK
WEN
WEN
the rising edge of WCLK and the rising edge of RCLK is less than t
REN
REN
SKEW2
PAE
HF
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus t
t
CLKH
t
ENS
n words in FIFO
n+1 words in FIFO
Figure 17. Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
t
CLKL
t
[
ENH
D-1
(2)
t
SKEW2
2
1
,
D/2 words in FIFO
(3)
Figure 18. Half-Full Flag Timing (IDT Standard and FWFT Modes)
+ 1
(4)
]
words in FIFO
t
t
PAE
CLKH
(1)
,
2
(2)
SKEW2
t
ENS
, then the PAE deassertion may be delayed one extra RCLK cycle.
t
CLKL
23
t
ENH
t
t
ENS
HF
n+1 words in FIFO
n+2 words in FIFO
t
ENS
[
D-1
D/2 + 1 words in FIFO
2
t
ENH
+ 2
]
(2)
(3)
words in FIFO
,
t
HF
1
(1)
,
(2)
COMMERCIAL AND INDUSTRIAL
t
PAE
TEMPERATURE RANGES
[
D-1
2
PAE
D/2 words in FIFO
2
+ 1
). If the time between
OCTOBER 22, 2008
]
words in FIFO
n words in FIFO
n+1 words in FIFO
4672 drw 21
4672 drw 20
(1)
,
(2)
(2)
,
(3)