HL82571EB Intel, HL82571EB Datasheet

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... Intel 82571EB/82572EI Ethernet ® Controller Specification Update April 2009 Revision 6.1 Order Number 321896-001 ...

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... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents that have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P ...

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Specification Update Revision History Revision Revision Date 1.0 Jan 2004 1.1 Jan 2004 1.2 Feb 2004 1.3 Mar 2004 1.4 Apr 2004 1.5 May 2004 1.6 Jun 2004 1.7 Jul 2004 1.8 Jan 2005 1.9 Jun 2005 2.0 Sep ...

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... Gigabit Ethernet Controller Product Preview Datasheet, Intel Corporation. • 82571EB/82572EI Gigabit Ethernet Controller Design Guide, Intel Corporation. • PCIe* Family of Gigabit Ethernet Controllers Software Developer's Manual, Intel Corporation This document is intended for hardware system manufacturers and software developers of applications, operating systems or tools ...

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Specification Update 2. Nomenclature This document uses various definitions, codes, and abbreviations to describe the Specification Changes, Errata, Sightings and/or Specification Clarifications that apply to the listed silicon/steppings: Table 2-1. Definitions Name Specification Modifications to the current published specifications. ...

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Codes and Abbreviations Name X Specification Change, Erratum, or Specification Clarification that applies to this stepping. Doc Document change or update that will be implemented. Fix This erratum is intended to be fixed in a future stepping of the ...

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... D0 (fiber applications) 82572EI D0 (SERDES backplane applications) *= Revision ID is located at Config address 0x8 bits 7:0 Top Marking Q-Specification JL82571EB Q866 HL82571EB Q864 JL82572EI Q867 HL82572EI Q865 JL82571EB N/A HL82571EB N/A JL82572EI N/A HL82572EI N/A Vendor Device ID ID 8086 105E 8086 105F 8086 1060 ...

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... Table 4-3. MM Numbers Product HL82571EB HL82572EI JL82571EB JL82572EI Figure 4-1. Example 82571EB/82572EI Identifying Marks Note: Lead-free parts will have “JL” as the prefix for the product code (vs. “HL”) and the “Q” designator refers to the Q Specification number in the table above. ...

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Specification Update 5. Summary Table of Changes No. D0 Plans 1 X Doc SMBus Operation at 1MHz Not Supported Doc iSCSI Header Split Is Not Supported The EEPROM Initialization Control 2 (word 0Fh) bit ...

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X NoFix 17 X NoFix 18 X NoFix 19 X NoFix 20 X NoFix 21 X NoFix 22 X NoFix 23 X NoFix 24 X NoFix 25 X NoFix 26 X NoFix 27 X NoFix 28 X NoFix 29 ...

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Specification Update No. D0 Plans ARC Halts when SMBus Sslave Address is Set to 0x00 Image Rx Packet NotificationTimeout Does Not Reset after Master 46 X Image Reads Fragment. BMC Configuration Commands are Discarded when there is ...

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X NoFix No. D0 Plans 1 X Doc No. D0 Plans 2 X Doc 3 X Doc 4 X Doc 5 X Doc 6 X Doc 7 X Doc 8 X Doc 9 X Doc 10 X Doc 11 ...

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Specification Update 6. Specification Changes 1. SMBus Operation at 1 Mhz Is Not Supported (400 kHz Operation Not Affected) Operation of the SMBus at 1 MHz is not supported. Operation at the standard SMBus frequency (400 kHz) is not ...

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Packet types supported by the packet split: The 82571/82572 provides header split for the packet types listed below. Other packet types are posted sequentially in the buffers of the packet split receive buffers. Packet Type 0x0 MAC , (VLAN/SNAP) Payload ...

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Specification Update Field Bit(s) IPFRSP_DIS 14 EXSTEN 15 IPv6_ExdIS 16 NEW_IPV6_EXT_DIs 17 3. The EEPROM Initialization Control 2 (word 0Fh) bit 7 is Reserved and Must Be Set To 0. The EEPROM Initialization Control 2 (word 0Fh) bit 7 ...

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... ECC Correction Enable 0 16 82571/82572 Specification Update Writing 1 to this bit clears the error counter and error 0 address fields When set, enables single bit ECC error correction. When 0 clear, ECC errors will be detected, but not corrected. Intel recommends that this bit be enabled. ...

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Specification Update 7. Errata 1. When Two Functions Have Differing MAX_PAYLOAD_SIZE, the Device Might Use the Larger Value For All Functions. Problem: MAX_PAYLOAD_SIZE is programmed per function. If two PCIe functions have different MAX_PAYLOAD_SIZE, the device might use the ...

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PCIe Differential- and Common-Mode Return Loss Is Higher Than Specified Value. Problem: The PCIe transmitter’s differential return loss instead of the -10 dB requirement. A PCIe Engineering Change Notice sets - the ...

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... Workaround: The driver must ensure that the first descriptor points to the (L2+L3+L4) Header and at least two bytes of the data (payload). This has been implemented in the Intel drivers. This workaround must be applied before activating TSO when MULR=1. Alternatively, register 0x3940 “TARC1” bit 22 can be set at initialization time to workaround this issue ...

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I C Transactions: When Working with Bus Speeds 400 KHz or Higher, the Bus Might Hang When the Master Reads More Bytes than the Slave Reported. Problem: When working in I device responds with a block of data ...

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... XOFF packet(s). Workaround: To minimize the likelihood of a Receive FIFO overrun, Receive Flow-Control Thresholds should be based on the expected maximum pause interval in the link partner’s XOFF packet. This has been implemented in the Intel drivers. Status: No Fix: There are no plans to fix this erratum. 21 ...

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Missed RX Packets. Problem: When the device operates with multiple-requests or Large Send enabled, there could be receive packet loss. When the Tx FIFO is full, the Tx flow may block the host DMA interface of the device. When ...

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... As the magic packet WoL uses RAR[0] only, magic packets to port 0 will not wake up the system. This has been implemented in the Intel drivers. The following information shows how the workaround can be implemented: • A boolean flag named laa_is_present is added to the adapter structure to identify to the driver that the workaround applied ...

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... Set the appropriate LAA in RAR[ (adapter->hw.mac_type == e1000_82571 && adapter->hw.laa_is_present) Intel drivers share some common functions, which have been adapted to this issue: • e1000_rar_set() is used to update the RAR registers. No changes are required to adapt to this issue, but it is the function used by the following functions. ...

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Specification Update /* Clear RAR[1-15] */ num_rar_entry = E1000_RAR_ENTRIES; /* Reserve a spot for the Locally Administered Address to work around if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE)) for(i = rar_used_count; i < num_rar_entry; i++) { } /* ...

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... RSS hash value to the stack. The TCP stack will calculate the RSS hash value for a TCP packet, which will prevent it from being dropped. This has been implemented in the Intel drivers. Status: No Fix: There are no plans to fix this erratum. ...

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Specification Update • In normal operation the comma used is k28.5; inverted disparity should not happen on a normal system. Workaround: None. Status: No Fix: There are no plans to fix this erratum. F 21. alse Detection of an ...

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Frames with Alignment Errors. Problem: The device discards a frame with extra bits. According to IEEE 802.3 2002 section 4.2.4.2.1, a frame containing a non-integer number of octets should be truncated to the nearest octet boundary. After the test ...

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Specification Update 27. 10base-T Link Pulse Hits the Template Mask Due to Voltage Ripple/Glitch Problem: The 10base-T link pulse touches the template due to voltage ripple/glitch. 29 ...

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Implication: Compliance with the specification is not complete, however, there is no effect at system level. Workaround: None. Status: No Fix: There are no plans to fix this erratum. 28. 10base-T TP_IDL Template Failure. Problem: The 10base-T TP_IDL waveform fails ...

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Specification Update 31. Reception of Undersized Frames Affects Good Frame Reception. Problem: If the device receives a one-byte fragment, then the following first-received frame will be discarded. Implication: After receiving a frame with a one-byte fragment, the device rejects ...

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Device Sends Only One XOFF Even if the Link Partner Has Timed Out and It Is Still Congested. Problem: When Flow Control is enabled, the device should periodically send XOFF packets as long congested to prevent ...

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... Workaround: Use an EEPROM image based on dev starter version. 5.9 or above. Status: Fixed in EEPROM dev starter version. 5.9 and above. Contact your Intel representative to ensure you have the latest EEPROM release. 39. Packets Received with an L2+L3 Header Length Greater than 256 Bytes Can Incorrectly Report a Checksum Error. ...

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... A power-saving feature when in Electrical-Idle for the PCIe bus, Receive is not enabled. Workaround: Use an EEPROM image based on dev starter version. 5.10 or above. Status: Fixed in EEPROM dev starter version. 5.10 and above. Contact your Intel representative to ensure you have the latest EEPROM release. 34 82571/82572 Specification Update ...

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... Workaround: Fixed in EEPROM dev starter image version 5.10 and above. This firmware will discard packets sent while the link is down after timeout. Contact your Intel representative to ensure you have the latest EEPROM release. Status: Fixed in EEPROM dev starter version. 5.12 and above. Contact your Intel representative to ensure you have the latest EEPROM release ...

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... Implication: Normal manageability traffic, such as KVM and Ping will halt in less than 15 minutes. Workaround: There is no workaround. Status: Fixed in EEPROM dev starter version. 5.12 and above. Contact your Intel representative to ensure you have the latest EEPROM release. 36 82571/82572 Specification Update ...

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... The BMC will attempt to recover packets by comparing bytes received with the original packet length. This process slows perforance. Workaround: No workaround. Status: Fixed in EEPROM dev starter version. 5.12 and above. Contact your Intel representative to ensure you have the latest EEPROM release. 51. SMBus Might Hang if the BMC Is Reset in the Middle of a Transaction. ...

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... Kg is NULL. Workaround: Use NULL password and NULL Kg, or always configure a Kg. Status: Fixed in EEPROM dev starter version. 5.12 and above. Contact your Intel representative to ensure you have the latest EEPROM release. 38 82571/82572 Specification Update ...

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... The 82571EB/82572EI uses the SIK instead of the K1 key (please refer to the IPMI 2.0 specification for more information on RAKP messages and keys). The Intel Redirection SDK has the same defect in it; as such, a RMCP+ session can be properly established using the SDK, however other utilities such as IPMITool will fail when a session is established due to the integrity check failure ...

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... Workaround: There is no work-around for this issue. Status: Fixed in EEPROM dev starter version. 5.12 and above. Contact your Intel representative to ensure you have the latest EEPROM release. 62. “Update User Password” Command Incorrectly Accepts Less ...

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Specification Update 64. Wakeup Event Occurs on Magic Packet that Doesn’t Pass Address Filter Problem: The 82571/82572 receives a magic packet that didn’t pass address filtering. The 82571/82572 will generate a wakeup event at the next packet if the ...

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Improperly Implements the Auto- Negotiation Advertisement Register. Problem: The 82571EB-82572EI improperly transmits the Link Code Word due to a write to register 4. The Link Code Word improperly switch immediately, which corresponds to a write to register 4. ...

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... In this case the second packet descriptor will not be written back until a new packet arrives. Implication: Receive packets may be delayed. Workaround: Do not use RDTR. RDTR is not used by Intel drivers. Use ITR. Status: No Fix 70. 82571/82572 Overwrites Transmit Descriptors in Internal Buffer ...

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Status: No Fix 71. Link Indication: LED Remains Power State in SerDes Mode. Problem: The LED might remain power state when SerDes power down is enabled (EEPROM word 0xF, bit 11; register CTRL_EXT 0x0018, ...

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... However, when using legacy interrupts and sharing interrupts between devices, the software may poll all the devices to find the source of the interrupt, including those devices that did not assert an interrupt. There may also be other situations in non-Intel drivers where ICR is polled even when no interrupt has been asserted. ...

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... Link may fail if Auto MDI-X is enabled during forced 100BASE-TX mode operation. Since the device does not disable this function automatically, the driver must perform this step. Auto MDI-X can be disabled by clearing PHYREG18.12. Intel’s software drivers have been implemented in this way. ...

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... PCIe output driver amplitude. If EEPROMs with the Manageability modes enabled have been used, please contact you Intel representative to ensure you have the latest EEPROM image required for your system. If you need an updated EEPROM image, it can be obtained from your Intel representative. Return loss spec line 47 ...

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... PCI Bus Power Management Interface Specification Revision 1.1 value of 375 mA on the 3.3Aux voltage rail. In order to always meet this specification, only one port should be enabled for WOL in the 82571EB. Intel Drivers limit the use of WOL to Port 0(Port A) of the 82571EB. ...

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... THERM_Dp (D4) and THEMR_Dn (D5) are reserved and should not be used. Clarification: In section 3.11 and Table 32 in the Intel Datasheet, are references to signals THERM_Dp (D4) and THEMR_Dn (D5), these pins are RESERVED and should not be used in any design. These pins should be left unconnected (floating). 12. ...

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When Port 0 and Port 1 Are Connected Back-to-Back, the PHY Should Be Reset As Part of the Driver Initialization To Avoid Link Failures. Clarification: If the PHY is not reset, then both ports might start the Auto-MDI-X protocol ...