EVAL-AD73322LEB Analog Devices Inc, EVAL-AD73322LEB Datasheet - Page 12

• Manufacturer Part Number: EVAL-AD73322LEB
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD73322LEB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

AD73322L
Decimation Filter
The digital filter used in the AD73322L carries out two important
functions. Firstly, it removes the out-of-band quantization
noise, which is shaped by the analog modulator and secondly,
it decimates the high frequency bit stream to a lower rate 16-
bit word.
The antialiasing decimation filter is a sinc-cubed digital filter
that reduces the sampling rate from DMCLK/8 to DMCLK/256,
and increases the resolution from a single bit to 15 bits or greater
(depending on chosen sampling rate). Its Z transform is given as:
where N is set by the sampling rate (N = 32 @ 64 kHz sam-
pling. . . N = 256 @ 8 kHz sampling). Thus when the sampling
rate is 64 kHz, a minimal group delay of 25 µs can be achieved.
F
F
F
B
B
F
B
B
= 4kHz
= 4kHz
= 4kHz
= 4kHz
F
F
SINTER
SFINAL
SIGNAL TRANSFER FUNCTION
[(1 – Z
= DMCLK/256
= 8kHz
–N
NOISE TRANSFER FUNCTION
)/(1 – Z
F
SINTER
–1
= DMCLK/256
)]
3
F
F
SINIT
SINIT
= DMCLK/8
= DMCLK/8
Word growth in the decimator is determined by the sampling
rate. At 64 kHz sampling, where the oversampling ratio between
sigma-delta modulator and decimator output equals 32, there
are five bits per stage of the three-stage Sinc3 filter. Due to symme-
try within the sigma-delta modulator, the LSB will always be a
zero; therefore, the 16-bit ADC output word will have 2 LSBs
equal to zero, one due to the sigma-delta symmetry and the
other being a padding zero to make up the 16-bit word. At
lower sampling rates, decimator word growth will be greater
than the 16-bit sample word, therefore truncation occurs in
transferring the decimator output as the ADC word. For example,
at 8 kHz sampling, word growth reaches 24 bits due to the OSR
of 256 between sigma-delta modulator and decimator output.
This yields eight bits per stage of the three-stage Sinc3 filter.
ADC Coding
The ADC coding scheme is in twos complement format (see
Figure 8). The output words are formed by the decimation
filter, which grows the word length from the single-bit output
of the sigma-delta modulator to a word length of up to 24 bits
(depending on decimation rate chosen), which is the final out-
put of the ADC block. In Data Mode this value is truncated to
16 bits for output on the Serial Data Output (SDO) pin.
In mixed Control/Data Mode, the resolution is fixed at 15 bits,
with the MSB of the 16-bit transfer being used as a flag bit to
indicate either control or data in the frame.
Decoder Channel
The decoder channels consist of digital interpolators, digital
sigma-delta modulators, single-bit digital-to-analog converters
(DAC), analog smoothing filters and programmable gain ampli-
fiers with differential outputs.
DAC Coding
The DAC coding scheme is in twos complement format with
0x7FFF being full-scale positive and 0x8000 being full-
scale negative.
ANALOG
ANALOG
INPUT
INPUT
V
V
V
V
REF
REF
REF
REF
+ (V
– (V
+ (V
– (V
REF
REF
REF
REF
0.32875)
0.32875)
0.6575)
0.6575)
V
REF
10...00
10...00
ADC CODE DIFFERENTIAL
ADC CODE SINGLE-ENDED
V
INN
V
V
V
INN
INP
INP
00...00
00...00
01...11
01...11