74LVC374APW-T NXP Semiconductors, 74LVC374APW-T Datasheet - Page 12

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74LVC374APW-T

Manufacturer Part Number
74LVC374APW-T
Description
Flip Flop D-Type Bus Interface Pos-Edge 3-ST 1-Element 20-Pin TSSOP T/R
Manufacturer
NXP Semiconductors
Datasheet

Specifications of 74LVC374APW-T

Package
20TSSOP
Logic Function
D-Type Bus Interface
Logic Family
LVC
Number Of Element Outputs
8
Output Signal Type
Single-Ended
Output Type
3-State
Number Of Output Enables Per Element
1
Typical Operating Supply Voltage
1.8|2.5|3.3 V
Operating Temperature
-40 to 125 °C
Philips Semiconductors
2003 May 14
handbook, full pagewidth
handbook, full pagewidth
Octal D-type flip-flop with 5 V tolerant inputs/outputs;
positive edge-trigger; 3-state
V
V
V
V
V
V
V
V
V
The shaded areas indicate when the input is permitted to change for predicable output performance.
M
M
X
X
Y
Y
M
M
OL
= V
= V
= V
= V
= 1.5 V at V
= 0.5V
= 1.5 V at V
= 0.5V
and V
OL
OL
OH
OH
+ 0.3 V at V
+ 0.1 V
CC
CC
OH
0.3 V at V
0.1 V
at V
at V
are the typical output voltage drop that occur with the output load.
CC
CC
CC
CC
CC
CC
at V
at V
< 2.7 V;
< 2.7 V;
2.7 V;
2.7 V;
CC
CC
CC
CC
2.7 V;
2.7 V;
< 2.7 V;
< 2.7 V.
Qn output
CP input
Dn input
HIGH-to-OFF
OFF-to-HIGH
LOW-to-OFF
OFF-to-LOW
Fig.9 Data setup and hold times for the Dn input to the CP input.
output
OE input
output
V
GND
GND
V OH
V OL
OL
V I
V I
GND
GND
V OH
and V
V CC
V OL
V I
Fig.8 3-state enable and disable times.
OH
are the typical output voltage drop that occur with the output load.
V M
V M
enabled
outputs
t PLZ
t PHZ
V M
t su
12
V X
t h
V Y
V M
disabled
outputs
t PZL
t PZH
t su
V M
V M
outputs
enabled
t h
MNA644
MNA202
Product specification
74LVC374A

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