LCMXO640C-3TN100I LATTICE SEMICONDUCTOR, LCMXO640C-3TN100I Datasheet - Page 93
LCMXO640C-3TN100I
Manufacturer Part Number
LCMXO640C-3TN100I
Description
CPLD MachXO Family 320 Macro Cells 1.8V/2.5V/3.3V 100-Pin TQFP Tray
Manufacturer
LATTICE SEMICONDUCTOR
Datasheet
1.LCMXO1200C-3FTN256I.pdf
(96 pages)
Specifications of LCMXO640C-3TN100I
Package
100TQFP
Family Name
MachXO
Number Of Macro Cells
320
Maximum Propagation Delay Time
4.9 ns
Number Of User I/os
74
Typical Operating Supply Voltage
1.8|2.5|3.3 V
Memory Type
SRAM
Operating Temperature
-40 to 100 °C
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LCMXO640C-3TN100I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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© 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
November 2007
For Further Information
A variety of technical notes for the MachXO family are available on the Lattice web site.
For further information on interface standards refer to the following web sites:
• TN1091,
• TN1089,
• TN1092,
• TN1090,
• TN1086,
• TN1087,
• TN1097,
• AN8066,
• JEDEC Standards (LVTTL, LVCMOS): www.jedec.org
• PCI: www.pcisig.com
MachXO sysIO Usage Guide
MachXO sysCLOCK Design and Usage Guide
Memory Usage Guide for MachXO Devices
Power Estimation and Management for MachXO Devices
MachXO JTAG Programming and Configuration User’s Guide
Minimizing System Interruption During Configuration Using TransFR Technology
MachXO Density Migration
Boundary Scan Testability with Lattice sysIO Capability
6-1
MachXO Family Data Sheet
Supplemental Information
DS1002 Further Information_01.2
Data Sheet DS1002
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