XC3S1500-5FGG456C Xilinx Inc, XC3S1500-5FGG456C Datasheet - Page 125
![no-image](/images/no-image-200.jpg)
XC3S1500-5FGG456C
Manufacturer Part Number
XC3S1500-5FGG456C
Description
FPGA Spartan®-3 Family 1.5M Gates 29952 Cells 725MHz 90nm Technology 1.2V 456-Pin FBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3r
Datasheet
1.XC3S50-4VQG100C.pdf
(217 pages)
Specifications of XC3S1500-5FGG456C
Package
456FBGA
Family Name
Spartan®-3
Device Logic Units
29952
Device System Gates
1500000
Maximum Internal Frequency
725 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
333
Ram Bits
589824
Number Of Logic Elements/cells
29952
Number Of Labs/clbs
3328
Total Ram Bits
589824
Number Of I /o
333
Number Of Gates
1500000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
456-BBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
NANO-SPARTAN - KIT NANOBOARD AND SPARTAN3 DC807-1001 - DAUGHTER CARD XILINX SPARTAN 3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S1500-5FGG456C
Manufacturer:
XilinxInc
Quantity:
3 000
Company:
Part Number:
XC3S1500-5FGG456C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC3S1500-5FGG456C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
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Table 86: VQ100 Package Pinout
Table 87: User I/Os Per Bank in VQ100 Package
DS099-4 (v2.5) December 4, 2009
Product Specification
Package Edge
Bank
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
7
7
7
7
Bottom
Right
Left
Top
R
IO_L23P_7
IO_L40N_7/VREF_7
IO_L40P_7
VCCO_7
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
Pin Name
XC3S200
XC3S50
I/O Bank
0
1
2
3
4
5
6
7
Maximum
VQ100 Pin
Number
I/O
10
6
7
8
8
8
8
8
P12
P11
P10
P20
P29
P41
P56
P66
P73
P82
P95
P33
P58
P84
P18
P8
P6
P3
P7
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCO
VREF
Type
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
I/O
I/O
www.xilinx.com
I/O
1
2
5
5
0
0
4
5
Table 86: VQ100 Package Pinout
User I/Os by Bank
Table 87
tributed between the eight I/O banks on the VQ100 pack-
age.
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
DUAL
Bank
N/A
N/A
N/A
0
0
0
0
6
6
0
0
All Possible I/O Pins by Type
indicates how the available user-I/O pins are dis-
Spartan-3 FPGA Family: Pinout Descriptions
VCCINT
VCCINT
VCCINT
CCLK
DONE
HSWAP_EN
M0
M1
M2
PROG_B
TCK
TDI
TDO
TMS
DCI
2
2
2
2
2
0
2
2
Pin Name
XC3S200
XC3S50
VREF
1
1
1
1
0
0
2
1
VQ100 Pin
Number
P100
P45
P69
P93
P52
P51
P98
P25
P24
P26
P99
P77
P76
P78
GCLK
CONFIG
CONFIG
CONFIG
CONFIG
CONFIG
CONFIG
CONFIG
VCCINT
VCCINT
VCCINT
2
2
0
0
2
2
0
0
JTAG
JTAG
JTAG
JTAG
Type
125
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