LFE2M35E-6FN256I LATTICE SEMICONDUCTOR, LFE2M35E-6FN256I Datasheet - Page 12
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LFE2M35E-6FN256I
Manufacturer Part Number
LFE2M35E-6FN256I
Description
FPGA LatticeECP2M Family 34000 Cells 90nm (CMOS) Technology 1.2V 256-Pin FBGA
Manufacturer
LATTICE SEMICONDUCTOR
Datasheet
1.LFE2-12SE-6FN256C.pdf
(389 pages)
Specifications of LFE2M35E-6FN256I
Package
256FBGA
Family Name
LatticeECP2M
Device Logic Units
34000
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
140
Ram Bits
2151424
In System Programmability
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2M35E-6FN256I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Table 2-5. DLL Signals
DLLDELA Delay Block
Closely associated with each DLL is a DLLDELA block. This is a delay block consisting of a delay line with taps and
a selection scheme that selects one of the taps. The DCNTL[8:0] bus controls the delay of the CLKO signal. Typi-
cally this is the delay setting that the DLL uses to achieve phase alignment. This results in the delay providing a cal-
ibrated 90° phase shift that is useful in centering a clock in the middle of a data cycle for source synchronous data.
The CLKO signal feeds the edge clock network. Figure 2-7 shows the connections between the DLL block and the
DLLDELA delay block. For more information, please see the list of additional technical documentation at the end of
this data sheet.
Figure 2-7. DLLDELA Delay Block
PLL/DLL Cascading
LatticeECP2/M devices have been designed to allow certain combinations of PLL (GPLL and SPLL) and DLL cas-
cading. The allowable combinations are:
• PLL to PLL supported
• PLL to DLL supported
CLKI
CLKFB
RSTN
ALUHOLD
UDDCNTL
DCNTL[8:0]
CLKOP
CLKOS
LOCK
Signal
GDLLFB_PIO
CLKFB_CK
DLL_PIO
PLL_PIO
Routing
Routing
CLKOP
ECLK1
I/O
O
O
O
O
I
I
I
I
I
Clock input from external pin or routing
Active high freezes the ALU
Synchronous enable signal (hold high for two cycles) from routing
Encoded digital control signals for PIC INDEL and slave delay calibration
The primary clock output
The secondary clock output with fine phase shift and/or division by 2 or by 4
Active high phase lock indicator
DLL feed input from DLL output, clock net, routing or external pin
Active low synchronous reset
* Software selectable
*
*
*
CLKI
CLKFB
CLKI
DCNTL[8:0]
DLLDELA Delay Block
2-9
DLL Block
Description
LatticeECP2/M Family Data Sheet
CLKOP
CLKOS
LOCK
CLKO
Architecture
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