PI6C487016FBE Pericom Semiconductor, PI6C487016FBE Datasheet - Page 2

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PI6C487016FBE

Manufacturer Part Number
PI6C487016FBE
Description
Clock Drivers & Distribution 1to16 LVCMOS/LVTTL Clock Drive
Manufacturer
Pericom Semiconductor
Type
Clock Dividerr
Datasheet

Specifications of PI6C487016FBE

Number Of Clock Inputs
2
Output Logic Level
LVCMOS/LVTTL
Output Frequency
250MHz
Operating Supply Voltage (min)
3.135V
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.465V
Package Type
LQFP
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Max Output Freq
250 MHz
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (max)
3.465 V
Supply Voltage (min)
3.135 V
Maximum Operating Temperature
+ 85 C
Package / Case
LQFP-48
Lead Free Status / RoHS Status
Compliant
Notes:
Function Table
Pin Descriptions
Number
1, 48
2
3, 4, 5, 6
7, 8, 9, 10
11
12, 16, 20, 24,
28, 32, 36, 40,
44
13, 15, 17, 19
14, 18
21, 23, 25, 27
22, 26
29, 31, 33, 35
30, 34
37, 39, 41, 43
38, 42
45
46
47
1. Pullup and Pulldown refer to internal input resistors. See Table 2, Pin characteristics, for typical values.
10-0008
nMR/OE
0
1
1
1
Name
V
CLK0
SELA :
SELD
ENA : END
nMR/OE
GND
QD0 : QD3
V
QC0 : QC3
V
QB0 : QB3
V
QA0 : QA3
V
CLK_SEL
nCLK1
CLK1
DD
DDOD
DDOC
DDOB
DDOA
Type
Power
Input
Input
Input
Input
Power
Output
Power
Output
Power
Output
Power
Output
Power
Input
Input
Input
Inputs
ENx
X
1
1
0
Pulldown
Pullup
Pullup
Pullup
Pullup
Pulldown
Pulldown
Description
Core supply pins (3.3V)
LVCMOS / LVTTL clock input
Controls frequency division for outputs. LVCMOS / LVTTL interface
levels. QAx:QDx
Output enable for QAx : QDx Outputs. Active HIGH. If pin is LOW,
outputs drive low. LVCMOS / LVTTL interface levels.
Master reset. When LOW, resets the ÷1/÷2 fl ip fl ops and sets the outputs
to high impedance. LVCMOS / LVTTL interface levels.
Supply Ground
Bank D Outputs, LVCMOS / LVTTL interface levels.
Voltage supply for QD0 : QD3
Bank C outputs, LVCMOS / LVTTL interface levels.
Voltage supply for QC0 : QC3
Bank B outputs, LVCMOS / LVTTL interface levels.
Voltage supply for QB0 : QB3
Bank A outputs, LVCMOS / LVTTL interface levels.
Voltage supply for QA0 : QA3
Clock select input, when HIGH, select CLK1, nCLK1 inputs. When
LOW, selects CLK0 input. LVCMOS / LVTTL interface levels.
Inverting differential clock input
Non-inverting differential clock input
SELx
X
X
0
1
2
LVCMOS/LVTTL Clock Driver
Bank X
Active
Active
Hi Z
Low
Outputs
Low Skew, 1-to-16
Qx Frequency
PS8741D
PI6C487016
F
N/A
N/A
F
IN
IN
/2
01/12/10

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