M48T201V-85MH1TR STMicroelectronics, M48T201V-85MH1TR Datasheet - Page 20

• Manufacturer Part Number: M48T201V-85MH1TR
• Manufacturer: STMicroelectronics

Specifications of M48T201V-85MH1TR

• Bus Type: Parallel
• User Ram: 512KB
• Operating Supply Voltage (typ): 3.3V
• Package Type: SOH
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 44
• Mounting: Surface Mount
• Date Format: DW:DM:M:Y
• Time Format: HH:MM:SS
• Lead Free Status / RoHS Status: Not Compliant

Clock operation
Figure 8.
3.6
Note:
20/37
V CC
V PFD (max)
V PFD (min)
V SO
AFE bit/ABE bit
AF bit in Flags Register
IRQ/FT
Backup mode alarm waveforms
Watchdog timer
The watchdog timer can be used to detect an out-of-control microprocessor. The user
programs the watchdog timer by setting the desired amount of timeout into the Watchdog
Register, address 7FFF7h. Bits BMB4-BMB0 store a binary multiplier and the two lower
order bits RB1-RB0 select the resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1
second, and 11 = 4 seconds. The amount of timeout is then determined to be the
multiplication of the five-bit multiplier value with the resolution. (For example: writing
00001110 in the watchdog register = 3*1 or 3 seconds).
Accuracy of timer is within ± the selected resolution.
If the processor does not reset the timer within the specified period, the M48T201Y/V sets
the WDF (watchdog flag) and generates a watchdog interrupt or a microprocessor reset.
WDF is reset by reading the flag register (address 7FFF0h).
The most significant bit of the watchdog register is the watchdog steering bit (WDS). When
set to a '0', the watchdog will activate the IRQ/FT pin when timed-out. When WDS is set to a
'1,' the watchdog will output a negative pulse on the RST pin for t
and the AFE, SQWE, ABE, and FT bits will reset to a '0' at the end of a watchdog timeout
when the WDS bit is set to a '1.'
The watchdog timer can be reset by two methods:
1.
2.
The timeout period then starts over. The WDI pin should be tied to V
watchdog will be reset on each transition (edge) seen by the WDI pin.
a transition (high-to-low or low-to-high) can be applied to the watchdog input pin (WDI)
or
the microprocessor can perform a WRITE of the watchdog register.
HIGH-Z
REC
. The watchdog register
M48T201Y, M48T201V
SS
if not used. The
AI03520
tREC
HIGH-Z