UPD4991ACX Renesas Electronics America, UPD4991ACX Datasheet - Page 27

• Manufacturer Part Number: UPD4991ACX
• Manufacturer: Renesas Electronics America

Specifications of UPD4991ACX

• Lead Free Status / RoHS Status: Supplier Unconfirmed

(4) CONTROL REGISTER 2 (address 0E
Control register 2 is used to monitor the BUSY signal, interval signal, and alarm status.
(b) TP2 control (when D
(a) BUSY FLAG
(b) ALARM FLAG
(c) INTERVAL FLAG
This is the count flag of the time counter. When this bit is 1, the time counter is in a count period. For
details, refer to (d) BUSY signal in 2.3.2 (2).
When this bit is 1, it indicates an alarm coincidence status; when it is 0, it indicates an alarm non-
coincidence status.
When this bit is 1, the interval output of TP2 is L; when it is 0, the interval output of TP2 is H.
Caution
If data is written to CONTROL REGISTER 2 in the alarm coincidence status, the ALARM FLAG may
be reset. To access CONTROL REGISTER 2 to write, therefore, be sure to check whether the alarm
coincidence or non-coincidence status is set (by reading the ALARM FLAG). In the alarm
coincidence status, set the ALARM FLAG, and then access CONTROL REGISTER 2 to write.
iii) INTERVAL STOP (D
ii) INTERVAL RESET (D
i) TP2 DISABLE (D
This bit controls output of TP2. When this bit is set, TP2 is forcibly turned off (high impedance)
regardless of the other operations.
When this bit is set, the interval timer is reset.
When this bit is set, the interval timer is stopped. If TP2 is low, however, the interval timer is stopped
30.5 s after the low period.
D
X
3
Table 2-7. CONTROL REGISTER 2 Status (R/O)
3
0
)
= 1)
2
)
1
)
CHAPTER 2 OPERATIONS
BUSY
FLAG
H
) [during read]
D
2
ALARM
FLAG
D
1
INTERVAL
FLAG
D
0
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