HS1-82C54RH-8 Intersil, HS1-82C54RH-8 Datasheet - Page 12

• Manufacturer Part Number: HS1-82C54RH-8
• Manufacturer: Intersil

Specifications of HS1-82C54RH-8

• Lead Free Status / RoHS Status: Supplier Unconfirmed

OUT low on the next CLK pulse, thus starting the one-shot
pulse N CLK cycles in duration. The one-shot is
retriggerable, hence OUT will remain low for N CLK pulses
after any trigger. The one-shot pulse can be repeated
without rewriting the same count into the Counter. GATE has
no effect on OUT.
If a new count is written to the Counter during a one-shot
pulse, the current one-shot is not affected unless the
Counter is retriggered. In that case, the Counter is loaded
with the new count and the one-shot pulse continues until
the new count expires.
NOTES:
Mode 2: Rate Generator
This Mode functions like a divide-by-N counter. It is typically
used to generate a Real Time Clock interrupt. OUT will
initially be high. When the initial count has decremented to 1,
26. Counters are programmed for binary (not BCD) counting and for
27. The Counter is always selected (CS always low).
28. CW stands for “Control Word”; CW = 10 means a Control Word
29. LSB stands for “Least significant byte” of count.
30. Numbers below diagrams are count values. The lower number is
31. N stands for an undefined count.
32. Vertical lines show transitions between count values.
GATE
GATE
GATE
OUT
OUT
OUT
CLK
CLK
CLK
reading/writing least significant byte (LSB) only.
of 10, Hex is written to the Counter.
the least significant byte. The upper number is the most
significant byte. Since the Counter is programmed to read/write
LSB only, the most significant byte cannot be read.
WR
WR
WR
CW = 12
CW = 12
CW = 12
N
N
N
N
N
N
LSB = 3
LSB = 3
LSB = 2
N
N
N
FIGURE 18. MODE 1
N
N
N
N
N
N
LSB = 4
12
0
3
0
3
0
2
0
2
0
2
0
1
0
1
0
1
0
0
FF
FF
0
0
0
3
FF
FF
FF
FE
0
2
0
3
0
1
0
4
0
2
0
0
0
3
HS-82C54RH
OUT goes low for one CLK pulse. OUT then goes high
again, the Counter reloads the initial count and the process
is repeated. Mode 2 is periodic; the same sequence is
repeated indefinitely. For an initial count of N, the sequence
repeats every N CLK cycles.
GATE = 1 enables counting; GATE = 0 disables counting. If
GATE goes low during an output pulse, OUT is set high
immediately. A trigger reloads the Counter with the initial
count on the next CLK pulse; OUT goes low N CLK pulses
after the trigger. Thus the GATE input can be used to
synchronize the Counter.
After writing a Control Word and initial count, the Counter will
be loaded on the next CLK pulse. OUT goes low N CLK
pulses after the initial count is written. This allows the
Counter to be synchronized by software also.
Writing a new count while counting does not affect the
current counting sequence. If a trigger is received after
writing a new count but before the end of the current period,
the Counter will be loaded with the new count on the next
CLK pulse and counting will continue from the new count.
Otherwise, the new count will be loaded at the end of the
current counting cycle.
NOTES:
33. Counters are programmed for binary (not BCD) counting and for
34. The Counter is always selected (CS always low).
35. CW stands for “Control Word”; CW = 10 means a Control Word
36. LSB stands for “Least significant byte” of count.
reading/writing least significant byte (LSB) only.
of 10, Hex is written to the Counter.
GATE
GATE
GATE
CLK
OUT
CLK
OUT
CLK
OUT
WR
WR
WR
CW = 14 LSB = 3
CW = 12 LSB = 3
CW = 14 LSB = 4
N
N
N
N
N
N
N
N
N
N
N
N
0
3
0
4
0
3
LSB = 5
0
2
0
2
0
3
0
1
0
2
0
2
0
3
0
3
0
1
0
2
0
2
0
5
0
1
0
1
0
4
0
3
0
3
0
3