MR82C54/B Intersil, MR82C54/B Datasheet
MR82C54/B
Specifications of MR82C54/B
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MR82C54/B Summary of contents
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... CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | 1-888-INTERSIL or 321-724-7143 Intersil (and design registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003. All Rights Reserved All other trademarks mentioned are the property of their respective owners. CMOS Programmable Interval Timer ...
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... Ordering Information PART NUMBERS 8MHz 10MHz CP82C54 CP82C54-10 IP82C54 IP82C54-10 CS82C54 CS82C54-10 IS82C54 IS82C54-10 CD82C54 CD82C54-10 ID82C54 ID82C54-10 MD82C54/B MD82C54-10/B MR82C54/B MR82C54-10/B SMD # 8406501JA - SMD# 84065013A - CM82C54 CM82C54-10 Functional Diagram DATA/ BUS BUFFER RD READ/ WR WRITE LOGIC CONTROL WORD REGISTER Pin Description ...
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Pin Description (Continued) DIP PIN SYMBOL NUMBER TYPE CLK CLOCK 2: Clock input of Counter 2. A0 ADDRESS: Select inputs for one of the three counters or Control Word Register for read/write ...
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Control Word Register The Control Word Register (Figure 2) is selected by the Read/Write Logic when A1 11. If the CPU then does a write operation to the 82C54, the data is stored in the Con- trol Word ...
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Operational Description General After power-up, the state of the 82C54 is undefined. The Mode, count value, and output of all Counters are undefined. How each Counter operates is determined when it is pro- grammed. Each Counter must be programmed before ...
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Possible Programming Sequence Control Word - Counter 0 Control Word - Counter 1 Control Word - Counter 2 LSB of Count - Counter 2 LSB of Count - Counter 1 LSB of Count - Counter 0 MSB of Count - ...
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Counters may be inserted between them. Another feature of the 82C54 is that reads and writes of the same Counter may be interleaved; for example, if the Counter is programmed for two ...
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OUTPUT NULL RW1 RW0 M2 COUNT D7 Out pin Out pin Null count 0 = Count available for reading Counter ...
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Both count and status of the selected counter(s) may be latched simultaneously by setting both COUNT and STA- TUS bits D5 This is functionally the same as issuing two separate read-back commands at once, and the above ...
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Mode 1: Hardware Retriggerable One-Shot OUT will be initially high. OUT will go low on the CLK pulse following a trigger to begin the one-shot pulse, and will remain low until the Counter reaches zero. OUT will then go high ...
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Mode 3: Square Wave Mode Mode 3 is typically used for Baud rate generation. Mode 3 is similar to Mode 2 except for the duty cycle of OUT. OUT will initially be high. When half the initial count has expired, ...
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LSB = 3 WR CLK GATE OUT LSB = 3 WR CLK GATE OUT ...
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Counter New counts are loaded and Counters are decremented on the falling edge of CLK. The largest possible initial count is 0; this is equivalent for binary counting and 10 for BCD counting. The counter does not ...
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Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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AC Electrical Specifications V CC SYMBOL PARAMETER READ CYCLE (1) TAR Address Stable Before RD (2) TSR CS Stable Before RD (3) TRA Address Hold Time After RD (4) TRR RD Pulse Width (5) TRD Data Delay from RD (6) ...
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Timing Waveforms DATA BUS DATA BUS RD, WR 82C54 (9) tWA (11) tAW (10) tSW VALID (13) tWD (14) tDW (12) tWW FIGURE 17. WRITE tRA (3) tAR (1) (2) ...
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Timing Waveforms (Continued) MODE WR CLK GATE OUT Burn-In Circuits VCC GND GND COUNT (SEE NOTE) tWC (28) (16) (17) tCLK tPWH (18) tPWL (19) tF (20) tGS tR (23) (24) (22) tGH tGL (27) tODG (26) tWO FIGURE 20. ...
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R1 GND F10 R1 F11 R1 F12 R2 F0 OPEN NOTES: = 5.5V ± 0. GND = 0V 3. VIH = 4.5V ±10% 4. VIL = -0. 47kΩ ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...