GD82559ER 824184 Intel, GD82559ER 824184 Datasheet - Page 46

• Manufacturer Part Number: GD82559ER 824184
• Manufacturer: Intel

Specifications of GD82559ER 824184

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Lead Free Status / RoHS Status: Not Compliant

GD82559ER — Networking Silicon
6.1.3
6.1.3.1
6.1.3.2
6.1.3.3
6.1.3.4
6.1.3.5
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100BASE-TX Receive Blocks
The receive subsection of the PHY unit accepts 100BASE-TX MLT-3 data on the receive
differential pair. Due to the advanced digital signal processing design techniques employed, the
PHY unit will accurately receive valid data from Category-5 (CAT5) UTP and Type 1 STP cable of
length well in excess of 100 meters.
Adaptive Equalizer
The distorted MLT-3 signal at the end of the wire is restored by the equalizer. The equalizer
performs adaptation based on the shape of the received signal, equalizing the signal to meet
superior Data Dependent Jitter performance.
Receive Clock and Data Recovery
The clock recovery circuit uses advanced digital signal processing technology to compensate for
various signal jitter causes. The circuit recovers the 125 MHz clock and data and presents the data
to the MLT-3 decoder.
MLT-3 Decoder, Descrambler, and Receive Digital Section
The PHY unit first decodes the MLT-3 data; afterwards, the descrambler reproduces the 5B
symbols originated in the transmitter. The descrambling is based on synchronization to the transmit
11-bit Linear Feedback Shift Register (LFSR) during idle. The data is decoded at the 4B/5B
decoder. Once the 4B symbols are obtained, the PHY unit outputs the receive data to the CSMA
unit.
100BASE-TX Receive Framing
The PHY unit does not differentiate between the fields of the MAC frame containing preamble,
start of frame delimiter, data and CRC. During 100 Mbps reception, the PHY unit differentiates
between the idle condition ("L" symbols on the wire) and the preamble or start of frame delimiter.
When two non-consecutive bits are 0b within 10 bits (125 Mbps 5B data coding) the PHY unit
immediately asserts carrier sense. When the “JK” symbols (“11000, 10001”) are fully recognized,
the PHY unit provides the received data to the CSMA unit. If the “JK” symbol is not recognized
(“false carrier sense”), the carrier sense is immediately de-asserted and a receive error is indicated.
100BASE-TX Receive Error Detection and Reporting
In 100BASE-TX mode, the PHY unit can detect errors in receive data in a number of ways. Any of
the following conditions is considered an error:
When any of the above error conditions occurs, the PHY unit immediately asserts its receive error
indication to the CSMA unit. The receive error indication is held active as long as the receive error
condition persists on the receive pair.
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Link integrity fails in the middle of frame reception.
The Start of Stream Delimiter (SSD) “JK” symbol is not fully detected after idle.
An invalid symbol is detected at the 4B/5B decoder.
Idle is detected in the middle of a frame (before “TR” is detected).
Datasheet