GD82559ER 824184 Intel, GD82559ER 824184 Datasheet - Page 50
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GD82559ER 824184
Manufacturer Part Number
GD82559ER 824184
Description
Manufacturer
Intel
Datasheet
1.GD82559ER_824184.pdf
(94 pages)
Specifications of GD82559ER 824184
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
196
Lead Free Status / RoHS Status
Not Compliant
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GD82559ER — Networking Silicon
6.3.1
6.3.2
44
Description
Auto-Negotiation selects the fastest operating mode (in other words, the highest common
denominator) available to hardware at both ends of the cable. A PHY’s capability is encoded by
bursts of link pulses called Fast Link Pulses (FLPs). Connection is established by FLP exchange
and handshake during link initialization time. Once the link is established by this handshake, the
native link pulse scheme resumes (that is, 10BASE-T or 100BASE-TX link pulses). A reset or
management renegotiate command (through the MDI interface) will restart the process. To enable
Auto-Negotiation, bit 12 of the MDI Control Register must be set. If the PHY unit cannot perform
Auto-Negotiation, it will set this bit to a 0 and determine the speed using Parallel Detection.
The PHY unit supports four technologies: 100BASE-Tx Full and Half Duplex and 10BASE-T Full
and Half Duplex. Since only one technology can be used at a time (after every re-negotiate
command), a prioritization scheme must be used to ensure that the highest common denominator
ability is chosen. Each bit in this table is set according to what the PHY is capable of supporting. In
the case of the 82559’s PHY unit, bits 0, 1, 2, 3, and 5 (10BASE-T, 10BASE-T full duplex,
100BASE-TX, 100BASE-TX full duplex and pause [frame based flow control], respectively) are
set.
To detect the correct technology, the two register fields, technology ability and technology priority,
should be ANDed together to obtain the highest common denominator. This value should then be
used to map into a priority resolution table used by the MAC driver to use the appropriate
technology.
Parallel Detect and Auto-Negotiation
The PHY unit automatically determines the speed of the link either by using Parallel Detect or
Auto-Negotiation. Upon a reset, a link status fail, or a Negotiate/Re-negotiate command, the PHY
unit inserts a long delay during which no link pulses are transmitted. This period, known as
Force_Fail, insures that the PHY unit‘s link partner has gone into a Link Fail state before Auto-
Negotiation or Parallel Detection begins. Thus, both sides (PHY unit and PHY unit’s link partner)
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