SI3011-F-FSR Silicon Laboratories Inc, SI3011-F-FSR Datasheet - Page 20

• Manufacturer Part Number: SI3011-F-FSR
• Manufacturer: Silicon Laboratories Inc

Specifications of SI3011-F-FSR

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Si3050 + Si3011
5. Functional Description
The Si3050 is an integrated direct access arrangement
(DAA) providing a programmable line interface that
meets global telephone line requirements. The Si3050
implements Silicon Laboratories’ patented isolation
capacitor technology, which offers the highest level of
integration by replacing an analog front end (AFE), an
isolation transformer, relays, opto-isolators, and a 2- to
4-wire hybrid with two highly-integrated ICs.
The Si3050+Si3011 chipset is software programmable
and designed to meet FCC and TBR21 specifications.
In addition, the Si3050 meets the most stringent global
requirements
immunity, high-voltage surges, and safety, including
FCC Parts 15 and 68, EN55022, EN55024, and many
other standards.
5.1. Line-Side Device Support
Three different line-side devices are available for use
with the Si3050 system-side device. This data sheet
covers the Si3011, which has been optimized for TBR21
and FCC-compliant countries. For information on a
globally-compliant solution, refer to the Si3050-Si3018/
19 data sheet.
5.2. Power Supplies
The Si3050 operates from a 3.3 V power supply. The
Si3050 input pins can only accept 3.3 V CMOS signal
levels. If support of 5 V signal levels is necessary, a
level shifter is required. The Si3011 derives its power
from two sources: the Si3050 and the telephone line.
The Si3050 supplies power over the patented isolation
capacitor link between the two devices, allowing the
Si3011 to communicate with the Si3050 while on-hook
and perform other on-hook functions, such as line
voltage monitoring. When off-hook, the Si3011 also
derives power from the line current supplied from the
telephone line. This feature is exclusive to DAAs from
Silicon Labs and allows the most cost-effective
implementation for a DAA while still maintaining robust
performance over all line conditions.
5.3. Initialization
Each time the Si3050 is powered up, assert the RESET
pin. When the RESET pin is deasserted, the registers
have default values to guarantee the line-side device
(Si3011) is powered down without the possibility of
loading the line (i.e., off-hook). An example initialization
procedure follows:
1. Power up and de-assert RESET.
2. Wait until the PLL is locked. This time is less than
20
1 ms from the application of PCLK.
for
out-of-band
energy,
emissions,
Rev. 1.11
3. Enable PCM (Register 33) or GCI (Register 42)
4. Set the desired line interface parameters (i.e., ILIM,
5. Set the FULL2 and IIRE bits as required.
6. Write a 0x00 into Register 6 to power up the
When this procedure is complete, the Si3011 is ready
for ring detection and off-hook operation.
5.4. Isolation Barrier
The Si3050 achieves an isolation barrier through
low-cost, high-voltage capacitors in conjunction with
Silicon
techniques.
eliminates
mismatches, common mode interference, or noise
coupling. As shown in the "2. Typical Application
Schematic" on page 17, the C1, C2, C8, and C9
capacitors isolate the Si3050 (system-side) from the
Si3011 (line-side). Transmit, receive, control, ring detect,
and caller ID data are passed across this barrier.
The communications link is disabled by default. To
enable it, the PDL bit (Register 6, bit 4) must be
cleared. No communication between the Si3050 and
Si3011 can occur until this bit is cleared. Allow the PLL
to lock to the PCLK and FSYNC input signals before
clearing the PDL bit.
5.5. Power Management
The Si3050 supports four basic power management
operation modes. The modes are normal operation,
reset operation, sleep mode, and full powerdown mode.
The power management modes are controlled by the
PDN and PDL bits (Register 6).
On powerup, or following a reset, the Si3050 is in reset
operation. The PDL bit is set, and the PDN bit is
cleared. The Si3050 is operational, except for the
communications link. No communication between the
Si3050 and line-side device (Si3011) can occur during
reset operation. Bits associated with the line-side device
are invalid in this mode.
In typical applications, the DAA will predominantly be
operated in normal mode. In normal mode, the PDL and
PDN bits are cleared. The DAA is operational and the
communications link passes information between the
Si3050 and the Si3011.
The Si3050 supports a low-power sleep mode that
supports ring validation and wake-up-on-ring features.
To enable the sleep mode, the PDN bit must be set.
mode.
DCR, ACIM, OHS2, TGA2, and TXG2[3:0]).
line-side device.
Laboratories’
signal
Differential
degradation
patented
capacitive
signal
from
communication
processing
capacitor