SI3011-F-FSR Silicon Laboratories Inc, SI3011-F-FSR Datasheet - Page 23

• Manufacturer Part Number: SI3011-F-FSR
• Manufacturer: Silicon Laboratories Inc

Specifications of SI3011-F-FSR

• Lead Free Status / RoHS Status: Supplier Unconfirmed

5.12. Line Voltage/Loop Current Sensing
The 5-bit LCS[4:0] register reports loop current
measurements when off-hook. An additional register is
available to report loop current to a finer resolution
(LCS2[7:0]). The LVS[7:0] register can be read when
the chipset is on or off hook. These registers can be
used to help determine the following line conditions:





5.12.1. Line Voltage Measurement
The Si3050 reports line voltage with the LVS[7:0] bits
(Register 29) in both on- and off-hook states with a
BITS
LCS
When on-hook, detect if a line is connected.
When on-hook, detect if a parallel phone is off-hook.
When off-hook, detect if a parallel phone goes on or
off-hook.
Detect if enough loop current is available to operate.
When used in conjunction with the OPD bit, detect if
an overload condition exists. (See "5.26. Overload
Detection" on page 31.)
30
25
20
15
10
5
0
0
3.3
6.6
9.9 13.2 16.5 19.8 23.1 26.4
Figure 19. Typical Loop Current LCS Transfer Function (ILIM = 0)
29.7
33
36.3 39.6 42.9 46.2 49.5 52.8 56.1 59.1 62.7 66
Loop Current (mA)
Rev. 1.11
resolution of 1 V per bit. The accuracy of these bits is
approximately ±10%. Bits 0 through 7 of this 8-bit
signed number indicate the value of the line voltage in
2s complement format. Bit 7 indicates the polarity of the
TIP/RING voltage.
If the INTE bit (Register 2, bit 7) and the POLM bit
(Register 3, bit 0) are set, a hardware interrupt is
generated on the AOUT/INT pin when Bit 7 of the LVS
register changes state. The edge-triggered interrupt is
cleared by writing 0 to the POLI bit (Register 4, bit 0).
The POLI bit is set each time bit 7 of the LVS register
changes state, and must be written to 0 to clear it. The
default state of the LVS register forces the LVS[7:0] bits
to 0 when the line voltage is 3 V or less. The LVFD bit
(Register 31, bit 0) disables this force-to-zero function
and allows the LVS register to display non-zero values
of
unpredictable values at line voltages between 0 to 2 V.
At 0 V, the LVS register displays all 0s.
3 V
69.3 72.6 75.9 79.2
and
82.5 85.8 89.1 92.4 95.7 99 102.3
below.
Si3050 + Si3011
This
Possible Overload
register
may
127
display
23