AD9875BSTZ Analog Devices Inc, AD9875BSTZ Datasheet - Page 15

• Manufacturer Part Number: AD9875BSTZ
• Manufacturer: Analog Devices Inc

Specifications of AD9875BSTZ

• Main Category: Single Chip
• Sub-category: Converter
• Power Supply Type: Analog/Digital
• Operating Supply Voltage (typ): 3.3V
• Package Type: LQFP
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 262mA
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Pin Count: 48
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

TRANSMIT PATH
The AD9875 transmit path consists of a Digital Interface Port,
a Programmable Interpolation Filter, and a Transmit DAC. All
clock signals required by these blocks are generated from the
f
below shows the interconnection between the major functional
components of the transmit path.
Digital Interface Port
The transmit Digital Interface Port has several modes of
operation. In its default configuration, the Tx Port accepts six
bit nibbles through the Tx[5:0] and TxSYNC pins and demul-
tiplexes the data into 12-bit words before passing it to the
Interpolation Filter. The input data is sampled on the rising
edge of f
Additional programming options for the Tx Port allow; sampling
the input data on the falling edge of f
abling of f
nibble widths of 5 bits/5 bits. Also, the Tx Port interface can be
controlled by the GAIN pin to provide direct access to the Rx
Path Gain Adjust register. All of these modes are fully described
in the Register Programming Definitions section of this data sheet.
The data format is two’s complement, as shown below:
The data can be translated to straight binary data format by
simply inverting the most significant bit.
The timing of the interface is fully described in the Transmit
Timing section of this data sheet.
PLL-A Clock Distribution
Figure 1 shows the clock signals used in the transmit path. The
DAC sampling clock, f
frequency equal to L × f
generated either by the crystal oscillator when a crystal is con-
nected between the OSCIN and XTAL pins, or by the clock that
is fed into the OSCIN pin, and L is the multiplier programmed
through the serial port. L can have the values of 1, 2, 4, or 8.
The transmit path expects a new half-word of data at the rate
of f
of the Tx port is:
REV. A
Tx QUIET
OSCIN
Tx SYNC
Tx [5:0]
011 . . 11: Maximum
000 . . 01: Midscale + 1 LSB
000 . . 00: Midscale
111 . . 11: Midscale – 1 LSB
111 . . 10: Midscale – 2 LSB
100 . . 00: Minimum
CLK-A
GAIN
CLK-A
signal by the PLL-A clock generator. The block diagram
. When the Tx multiplexer is enabled, the frequency
CLK-A
CLK-A
Figure 1. Transmit Path Block Diagram
f
CLK A
DEMUX
.
Tx
, reversing the order of the nibbles, and inputting
−
f
CLK-A
= ×
10
2
DAC
OSCIN
Kx INTERPOLATION
f
CLOCK GEN
DAC
, is generated by DPLL-A. f
LPF/BPF
, where f
PLL-A
K
L
= ×
2
f
CLK–A
OSCIN
DAC
L
= L
×
10
, inversion or dis-
is the internal signal
f
OSCIN
f
OSCIN
AD9875
TxDAC+
f
OSCIN
K
DAC
has a
Tx+
Tx–
OSCIN
XTAL
–15–
where K is the interpolation factor that can be programmed to
be 1, 2, or 4.
When the Tx multiplexer is disabled, the frequency of the Tx port is:
Interpolation Filter
The interpolation filter can be programmed to run at 2× and 4×
upsampling ratios in each of three different modes. The transfer
functions of these six configurations are shown in TPCs 1–6.
The X-axis of each of these figures corresponds to the frequency
normalized to f
discrete time transfer function of the interpolation filters alone
and with the SIN(x)/x transfer function of the DAC. The Inter-
polation Filter can also be programmed into a pass-through mode
if no interpolation filtering is desired.
The contents of the interpolation filters are not cleared by
hardware or software resets. It is recommended to “flush” the
transmit data path with zeros before transmitting data.
Table I contains the following parameters as a function of the
mode that it is programmed:
Latency – the number of clock cycles from the time a digital
impulse is written to the DAC until the peak value is output at
the Tx± pins.
Flush – the number of clock cycles from the time a digital
impulse is written to the DAC until the output at the Tx± pins
settles to zero.
f
cutoff frequency of the interpolation filter as a fraction of f
the DAC sampling frequency.
f
cutoff frequency of the interpolation filter as a fraction of f
the DAC sampling frequency.
Register 7[7:4] 0
Mode
Latency, f
Clock Cycles
Flush, f
Clock Cycles
f
f
f
f
D/A Converter
The AD9875 DAC provides differential output current on the
Tx+ and Tx– pins. The value of the output currents are compli-
mentary, meaning that they will always sum to I
current of the DAC. For example, when the current from Tx+ is
at full-scale, the current from Tx– is zero. The two currents will
LOWER
UPPER
LOWER,
UPPER,
LOWER,
UPPER,
0.1 dB
3 dB
(0.1 dB, 3 dB) – This indicates the upper 0.1 dB or 3 dB
Table I. Interpolation Filter Parameters vs. Mode
DAC
0.1 dB
3 dB
(0.1 dB, 3 dB) – This indicates the lower 0.1 dB or 3 dB
DAC
f
DAC
4 × LPF 2 × LPF 4 × BPF 2 × BPF 4 × BPF 4 × BPF
86
128
0
0.102
0
0.119
CLK A
0
. These transfer functions show both the
−
=
0
30
48
0
0.204
0
0.238
f
DAC
1
K
0
Adj.
86
128
0.398
0.602
0.381
0.619
=
L
4
×
f
0
Adj.
30
48
0.276
0.724
0.262
0.738
OSCIN
5
K
AD9875
FS
0
Lower
86
142
0.148/
0.774
0.226/
0.852
0.131/
0.757
0.243/
0.869
, the full-scale
8
0
Upper
86
142
0.274/
0.648
0.352/
0.762
0.257/
0.631
0.369/
0.743
DAC
DAC
C
,
,