AD9875-EB Analog Devices Inc, AD9875-EB Datasheet
AD9875-EB
Specifications of AD9875-EB
Related parts for AD9875-EB
AD9875-EB Summary of contents
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... The AD9875 ADC and/or DAC can also be used at higher sampling rates as high as 64 MSPS in a 5-bit resolution non- multiplexed mode. The AD9875 is pin compatible with the 12-bit AD9876. Both are available in a space-saving 48-lead LQFP package. They are specified over the industrial (–40°C to +85°C) temperature range. ...
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... Output Offset Differential Nonlinearity Integral Nonlinearity Output Capacitance Phase Noise @ 1 kHz Offset, 10 MHz Signal Signal-to-Noise and Distortion (SINAD) 10 MHz Analog Out AD9875 (20 MHz BW) Wideband SFDR (to Nyquist, 64 MHz Max) 5 MHz Analog Out 10 MHz Analog Out Narrowband SFDR (3 MHz Window) 10 MHz Analog Out IMD ( ...
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... Maximum Programmable Gain (12 MHz Filter) (26 MHz Filter) Gain Step Size Gain Step Accuracy Gain Range Error Offset Error, PGA Gain = 0 dB (AD9875) Absolute Gain Error, PGA Gain = PATH INPUT CHARACTERISTICS Input Voltage Range Input Capacitance Differential Input Resistance Input Bandwidth (–3 dB) Input Referred Noise (at +36 dB Gain with Filter) 25° ...
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... AD9875 –SPECIFICATIONS Parameter Tx PATH INTERFACE Maximum Input Nibble Rate, 2× Interpolation Tx-Set Up Time ( Tx-Hold Time ( PATH INTERFACE Maximum Output Nibble Rate Rx-DataValid Time ( Rx-Data Hold Time ( CMOS LOGIC INPUTS Logic “1” Voltage Logic “0” Voltage Logic “1” Current Logic “ ...
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... Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Model Temperature Range AD9875BST –40°C to +85°C AD9875-EB –40°C to +85°C AD9875BSTRL –40°C to +85°C CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection ...
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... ADC Reference Decoupling Node ADC Reference Decoupling Node Receive Path + Input Receive Path – Input Crystal Oscillator Inverter Output PIN CONFIGURATION OSCIN 1 PIN 1 SENABLE 2 IDENTIFIER SCLK 3 SDATA 4 AVDD 5 AD9875 AVSS 6 TOP VIEW Tx+ 7 (Not to Scale) Tx– 8 AVSS 9 FSADJ 10 11 REFIO PWR –6– 36 DRVSS ...
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... The ADC output codes’ standard deviation is calculated in LSB, and converted to an equivalent voltage. This results in a noise figure that can be directly referred to the Rx input of the AD9875. SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD) SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc ...
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... AD9875 –Typical Tx Digital Filter Performance Characteristics 10 0 INTERPOLATION –10 FILTER –20 –30 –40 INCLUDING SIN(X)/X –50 –60 –70 –80 –90 –100 0.0 0.1 0.2 0.3 0.4 0.5 0.6 NORMALIZED – TPC 1. 4 Low-Pass Interpolation Filter 10 INTERPOLATION 0 FILTER –10 –20 INCLUDING SIN(X)/X – ...
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... MHz and 7.1 MHz, 4 OUT 10 –10 –20 –30 = 32MSPS DATA –40 –50 –60 –70 –80 –90 –100 MSPS TPC 12. Dual Tone Spectral Plot @ f DATA f = 6.9 MHz and 7.1 MHz, 2 OUT –9– AD9875 = 100 ) DAC f = 50MSPS DATA f = 50MSPS DATA – MHz OUT @ f ...
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... AD9875 Typical AC Characteristics Curves for TxDAC 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 – FREQUENCY OFFSET – kHz TPC 13. Phase Noise Plot @ MHz, 4 LPF OUT 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –1 ...
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... TPC 19 MHz, LPF with Wideband Rx LPF = 0 2.5 2.4 2.3 2.2 2.1 2.0 1.9 1.8 1.7 1.6 1.5 –11– AD9875 112 128 144 160 vs. Tuning Target MHz, LPF with C ADC –6 –4 – VGA GAIN – dB TPC 20. PGA Gain Step Size vs. Gain ...
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... AD9875 Typical AC Characterization Curves for Rx Path LOG MAG 5dB/REF 0dB 0 1MHz 10MHz TPC 21. Rx LPF Frequency Response, Low f Tuning Targets LOG MAG 5dB/REF 0dB 1MHz 10MHz TPC 22. Rx LPF Frequency Response, High f Tuning Targets LOG MAG 5dB/REF 0dB 0 1MHz 10MHz TPC 23. Rx LPF Frequency Response, Low f ...
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... ADC 700 650 600 TPC 32. Rx Path Setting, 1/2 Scale Falling Step with Gain Change –13– AD9875 5ns/REF 0s 29.97ns 29.5MHz 0 10MHz 100MHz , 0 60 and 0 C FILTER ENABLED FILTER BYPASSED – GAIN SETTING MSPS, ...
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... AD9875 Typical AC Characterization Curves for Rx Path 10.0 9.5 f OSCIN 9.0 8.5 f PLLB/2 8.0 7.5 7 – MHz S TPC 33. Rx Path ENOB vs. f ADC 10.0 f OSCIN 9.5 9.0 8.5 f PLLB/2 8.0 7.5 7 – MHz IN TPC 36. Rx Path ENOB vs 10.0 9.5 f POSCIN 9.0 f PLLB/2 8 ...
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... TRANSMIT PATH The AD9875 transmit path consists of a Digital Interface Port, a Programmable Interpolation Filter, and a Transmit DAC. All clock signals required by these blocks are generated from the f signal by the PLL-A clock generator. The block diagram OSCIN below shows the interconnection between the major functional components of the transmit path ...
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... Tx+ Tx– ADC ) × R The AD9875’s analog-to-digital converter implements a pipelined L multistage architecture to achieve high sample rates while con- suming low power. The ADC distributes the conversion over R several smaller A/D subblocks, refining the conversion with L progressively higher accuracy as it passes the results from stage to stage ...
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... HPF function is not desired, the HPF can be bypassed and the latency will not be incurred. Clock and Oscillator Circuitry The AD9875’s internal oscillator generates all sampling clocks from a fundamental frequency quartz crystal. Figure 3a shows how the quartz crystal is connected between OSCIN (Pin 1) and XTAL (Pin 48) with parallel resonant load capacitors as specified by the crystal manufacturer ...
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... Tx [5:0] GAIN Receive Port Timing The AD9875 receives port consists of a six bit data bus Rx[5:0], a clock and an Rx SYNC signal. Two consecutive nibbles of the Rx data are multiplexed together to form a 10-bit data word. The Rx data is valid on the rising edge of CLK-A when the ...
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... AD9875 and to run the internal state machines. SCLK maximum frequency is 25 MHz. All data transmitted to the AD9875 is sampled on the rising edge of SCLK. All data read from the AD9875 is validated on the rising edge of SCLK and is updated on the falling edge. SENABLE—Serial Interface Enable The SENABLE pin is active low ...
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... SENABLE went active. On every eighth rising edge of SCLK byte is transferred over the SPI. During a multibyte write cycle, this means the registers of the AD9875 are not simultaneously updated, but occur sequentially. For this reason recom- mended that single byte transfers be used when changing the SPI configuration or performing a software reset ...
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... Setting this bit high bypasses the 4-pole LPF. The filter is automatically powered down when this bit is set. Bit 1: Enable 1-Pole Rx LPF The AD9875 can be configured with an additional 1-pole ~16 MHz provides the input filter for applications that require steeper filter roll-off or CLKIN want to use the 1-pole filter instead of the 4-pole receive Low-Pass filter ...
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... The data is always aligned to the MSB pin Tx[5]. Enabling this pin on the AD9875 allows for a five pin versus the default six pin interface. Bit 2: Transmit Port Least Significant Nibble First Setting Bit 2 high reconfigures the AD9875 for a transmit mode that expects least significant nibble before the most significant nibble ...
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... V digital logic circuits, a DVDD section used to supply the digital supply pins of the AD9875, an AVDD section used to supply the analog supply pins of the AD9875, and a VANLG section that supplies the higher voltage analog components on the board. The 3VDD ...
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... ESR, bulk decoupling capacitor on the MxFE side of the ferrite as well as a low ESR, ESL decoupling capacitors on each supply pin (i.e., the AD9875 requires five power supply decoupling caps, one each on Pins 5, 38, 47, 14, and 35). The decoupling caps should be placed as close to the MxFE supply pins as possible ...
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... Dimensions shown in millimeters 1.60 MAX PIN 1 INDICATOR 0.75 0.60 0.45 1 SEATING PLANE 0.20 0.09 VIEW 0.08 MAX COPLANARITY 0.50 VIEW A BSC COMPLIANT TO JEDEC STANDARDS MS-026BBC –25– AD9875 9.00 BSC TOP VIEW 7.00 BSC (PINS DOWN 0.27 0.22 0.17 ...
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... AD9875 Revision History Location 8/02—Data Sheet changed from REV REV. A. Changes to Table .20 Changes to REGISTER 3–CLOCK SOURCE CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 ST-48 package updated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 –26– Page REV. A ...
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