AD9875-EB Analog Devices Inc, AD9875-EB Datasheet - Page 23

• Manufacturer Part Number: AD9875-EB
• Description: BOARD EVAL FOR AD9875
• Manufacturer: Analog Devices Inc

Specifications of AD9875-EB

• Rohs Status: RoHS non-compliant
• Module/board Type: Evaluation Board
• For Use With/related Products: AD9875
• Lead Free Status / Rohs Status: Not Compliant

REV. A
Bit 3: Power-Down Interpolator at TxQUIET Pin Low
Setting Bit 3 high enables the TxQUIET pin to shut off the
DAC output. If the bit is set to one, then pulling the TxQUIET
pin low will power down the interpolator filters. In most appli-
cations the interpolator filter will need to be flushed with zeros
before or after being powered down.
Bit 4 to Bit 7: Interpolation Filter Select
Bits 4 to 7 define the Interpolation filter characteristic and inter-
polation rate.
Bits 7:4;
The interpolation factor has a direct influence on the CLK-A
output frequency. When the transmit input data multiplexer is
enabled (10-bit mode):
where K is the interpolation factor.
When the transmit input data multiplexer is disabled (5-/6-bit
mode):
where K is the interpolation factor.
REGISTER 8—RECEIVER AND CLOCK OUTPUT SETTINGS
Bit 0: Rx Port Multiplexer Bypass
Setting this bit high bypasses the Rx port output multiplexer.
This will output only the 6 MSBs of the ADC word. This mode
enables ADC sampling rates above 55 MSPS.
Bit 1: Rx Port Width Five Bits
If the bit is set high, the Rx port data will be output in two
nibbles of five bits each (on pins Rx[5:1]). When this bit is low
(default), the most significant nibble will contain six bits and the
least significant nibble will have four bits. The default mode
makes the AD9875 pin compatible with the AD9876.
Bit 2: Rx Port LS Nibble First
Reconfigures the AD9875 for a receive mode that expects less
significant bits before the most significant bits.
Bit 3: Three-State Rx Port
This bit sets the receive output Rx[5:0] into a high impedance
three-state mode. It allows for sharing the bus with other devices.
Bit 4, Bit 5: Disable CLK-A, Disable CLK-B
Setting Bit 4 or Bit 5 stops CLK-A or CLK-B respectively, from
toggling. The output is held to a logic 0 level.
Bit 4, Bit 5: Disable CLK-A, Disable CLK-B
Setting Bit 4 or Bit 5 fixes CLK-A or CLK-B to a low output
level, respectively.
Bit 6: CLK-A Output Invert
Setting Bit 6 high inverts the CLK-A output signal.
Bit 7: CLK-B Output Invert
Setting this bit high inverts the CLK-B output signal. This effectively
changes the timing of the Rx[5:0] and RxSYNC signals from rising
edge triggered to falling edge triggered with respect to the CLK-B
signal.
0 × 2; Interpolation Bypass.
0 × 0; see TPC 1. 4× Interp, LPF.
0 × 1; see TPC 2. 2× Interp, LPF.
0 × 4; see TPC 3. 4× Interp, BPF, Adj image.
0 × 5; see TPC 4. 2× Interp, BPF, Adj image.
0 × 8; see TPC 5. 4× Interp, BPF, lower image.
0 × C; see TPC 6. 4× Interp, BPF, upper image.
f
CLK A
f
CLK A
−
−
= ×
2
=
f
DAC
f
DAC
K
K
–23–
REGISTER F—DIE REVISION
This register stores the die revision of the chip. It is a read-
only register.
PCB DESIGN CONSIDERATIONS
Although the AD9875 is a mixed-signal device, the part should
be treated as an analog component. The digital circuitry on-chip
has been specially designed to minimize the impact that the
digital switching noise will have on the operation of the analog
circuits. Following the power, grounding and layout recommen-
dations in this section will help you get the best performance
from the MxFE.
Component Placement
If the three following guidelines of component placement are
followed, chances for getting the best performance from the
MxFE are greatly increased. First, manage the path of return
currents flowing in the ground plane so that high frequency
switching currents from the digital circuits do not flow on the
ground plane under the MxFE or analog circuits. Second, keep
noisy digital signal paths and sensitive receive signal paths as
short as possible. Third, keep digital (noise generating) and
analog (noise susceptible) circuits as far away from each other
as possible.
In order to best manage the return currents, pure digital circuits
that generate high switching currents should be closest to the
power supply entry. This will keep the highest frequency return
current paths short, and prevent them from traveling over the
sensitive MxFE and analog portions of the ground plane. Also,
these circuits should be generously bypassed at each device
which will further reduce the high frequency ground currents.
The MxFE should be placed adjacent to the digital circuits,
such that the ground return currents from the digital sections
will not flow in the ground plane under the MxFE. The analog
circuits should be placed furthest from the power supply.
The AD9875 has several pins which are used to decouple sensi-
tive internal nodes. These pins are REFIO, REFB, and REFT.
The decoupling capacitors connected to these points should
have low ESR and ESL. These capacitors should be placed as
close to the MxFE as possible and be connected directly to the
analog ground plane.
The resistor connected to the FSADJ pin should also be placed
close to the device and connected directly to the analog ground plane.
Power Planes and Decoupling
The AD9875 evaluation board demonstrates a good power supply
distribution and decoupling strategy. The board has four layers;
two signal layers, one ground plane and one power plane. The
power plane is split into a 3VDD section used for the 3 V digital
logic circuits, a DVDD section used to supply the digital supply
pins of the AD9875, an AVDD section used to supply the analog
supply pins of the AD9875, and a VANLG section that supplies
the higher voltage analog components on the board. The 3VDD
section will typically have the highest frequency currents on the
power plane and should be kept the furthest from the MxFE and
analog sections of the board. The DVDD portion of the plane
brings the current used to power the digital portion of the MxFE
to the device. This should be treated similarly to the 3VDD power
plane and be kept from going underneath the MxFE or analog
components. The MxFE should largely sit on the AVDD portion
of the power plane.
AD9875