LAN83C185-JT Standard Microsystems (SMSC), LAN83C185-JT Datasheet - Page 17

• Manufacturer Part Number: LAN83C185-JT
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN83C185-JT

• Lead Free Status / RoHS Status: Compliant

High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
Datasheet
SMSC LAN83C185
GROUP
CODE
01001
10100
10101
01010
10010
10001
00100
00000
00001
01011
10011
10110
11010
11000
01101
00110
11001
11110
01110
01111
10111
11011
11100
11101
00111
11111
The encoding process may be bypassed by clearing bit 6 of register 31. When the encoding is
bypassed the 5
Note that encoding can be bypassed only when the MAC interface is configured to operate in MII
mode.
SYM
A
B
C
D
E
R
H
V
V
V
V
0
1
2
3
4
5
6
7
8
9
F
K
T
J
I
th
IDLE
First nibble of SSD, translated to “0101”
following IDLE, else RX_ER
Second nibble of SSD, translated to
“0101” following J, else RX_ER
First nibble of ESD, causes de-assertion
of CRS if followed by /R/, else assertion
of RX_ER
Second nibble of ESD, causes
deassertion of CRS if following /T/, else
assertion of RX_ER
Transmit Error Symbol
INVALID, RX_ER if during RX_DV
INVALID, RX_ER if during RX_DV
INVALID, RX_ER if during RX_DV
INVALID, RX_ER if during RX_DV
transmit data bit is equivalent to TX_ER.
C
D
A
B
E
F
0
1
2
3
4
5
6
7
8
9
INTERPRETATION
Table 4.1 4B/5B Code Table
RECEIVER
0000
0001
0010
0100
0101
1000
1001
1010
1101
0011
0110
0111
1011
1100
1110
1111
DATASHEET
17
DATA
Sent after /T/R until TX_EN
Sent for rising TX_EN
Sent for rising TX_EN
Sent for falling TX_EN
Sent for falling TX_EN
Sent for rising TX_ER
INVALID
INVALID
INVALID
INVALID
C
D
A
B
E
F
0
1
2
3
4
5
6
7
8
9
INTERPRETATION
TRANSMITTER
0000
0001
0010
0011
0100
0101
0110
1000
1001
1010
1011
1100
1101
0111
1110
1111
Revision 0.8 (06-12-08)
DATA