LAN83C185-JT Standard Microsystems (SMSC), LAN83C185-JT Datasheet - Page 59

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LAN83C185-JT

Manufacturer Part Number
LAN83C185-JT
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet

Specifications of LAN83C185-JT

Lead Free Status / RoHS Status
Compliant

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0
High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
Datasheet
SMSC LAN83C185
Peak Differential Output Voltage High
Peak Differential Output Voltage Low
Signal Amplitude Symmetry
Signal Rise & Fall Time
Rise & Fall Time Symmetry
Duty Cycle Distortion
Overshoot & Undershoot
Jitter
Transmitter Peak Differential Output Voltage
Receiver Differential Squelch Threshold
PIN NO.
16
17
19
20
46
Note 6.1
Note 6.2
Note 6.3
Note 6.4
PARAMETER
PARAMETER
Table 6.9 Internal Pull-Up / Pull-/Down Configurations (continued)
SPEED100
Measured at the line side of the transformer, line replaced by 100 Ω (+/- 1%) resistor.
Offset from16 nS pulse width at 50% of pulse peak
Measured differentially.
Min/max voltages guaranteed as measured with 100 Ω resistive load.
FDUPLEX
ACTIVITY
LINKON
NAME
nINT
Table 6.10 100Base-TX Transceiver Characteristics
Table 6.11 10BASE-T Transceiver Characteristics
SYMBOL
V
V
T
D
V
V
T
PPH
RFS
PPL
DATASHEET
RF
OS
SS
CD
SYMBOL
V
V
PULL-UP OR PULL-DOWN
OUT
DS
59
-950
MIN
950
3.0
98
35
-
-
Pull-up
Pull-up
Pull-up
Pull-up
Pull-up
MIN
300
2.2
TYP
50
-
-
-
-
-
-
TYP
420
2.5
-1050
MAX
1050
102
5.0
0.5
1.4
65
5
MAX
585
2.8
UNITS
mVpk
mVpk
nS
nS
nS
UNITS
%
%
%
mV
Revision 0.8 (06-12-08)
V
TYPE
30 uA
30 uA
30 uA
30 uA
30 uA
Note 6.1
Note 6.1
Note 6.1
Note 6.1
Note 6.1
Note 6.2
Note 6.3
NOTES
Note 6.4
NOTES

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