KSZ8041TL A3 TR Micrel Inc, KSZ8041TL A3 TR Datasheet
KSZ8041TL A3 TR
Specifications of KSZ8041TL A3 TR
Related parts for KSZ8041TL A3 TR
KSZ8041TL A3 TR Summary of contents
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... The KSZ8041TL represents a new level of features and Functional Diagram KSZ8041TL/FTL LinkMD is a registered trademark of Micrel, Inc. Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 ( December 2009 KSZ8041TL/FTL/MLL 10Base-T/100Base-TX/100Base-FX Physical Layer Transceiver Data Sheet Rev ...
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... Micrel, Inc. Features x Single-chip 10Base-T/100Base-TX physical layer solution x Fully compliant to IEEE 802.3u Standard x Low power CMOS design, power consumption of <180mW x HP auto MDI/MDI-X for reliable detection and correction for straight-through and crossover cables with disable and enable option x Robust operation over standard cables x LinkMD ® ...
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... Added maximum MDC clock speed. Added 40K +/-30% to note 1 of Pin Description and Strapping Options tables for internal pull-ups/pull- downs. Changed Model Number in Register 3h – PHY Identifier 2. Changed polarity (swapped definition) of DUPLEX strapping pin. Removed DUPLEX strapping pin update to Register 4h – Auto-Negotiation Advertisement bits [8, 6]. ...
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Micrel, Inc. Contents General Description .............................................................................................................................................................. 1 Functional Diagram............................................................................................................................................................... 1 Features ................................................................................................................................................................................. 2 Applications........................................................................................................................................................................... 2 Ordering Information ............................................................................................................................................................ 2 Revision History.................................................................................................................................................................... 3 List of Figures........................................................................................................................................................................ 6 List of Tables ......................................................................................................................................................................... 7 Pin Configuration – KSZ8041TL .......................................................................................................................................... 8 Pin Configuration – ...
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Micrel, Inc. SMII Signal Definition (KSZ8041TL/FTL only).................................................................................................................. 29 Clock Reference (CLOCK) ......................................................................................................................................... 29 Sync Pulse (SYNC) ..................................................................................................................................................... 29 Transmit Data and Control (TX) ................................................................................................................................ 29 Receive Data and Control (RX).................................................................................................................................. 30 Collision Detection ..................................................................................................................................................... 31 HP Auto MDI/MDI-X.......................................................................................................................................................... 32 Straight ...
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Micrel, Inc. List of Figures Figure 1. Auto-Negotiation Flow Chart................................................................................................................................. 24 Figure 2. SMII Transmit Data/Control Segment................................................................................................................... 30 Figure 3. SMII Receive Data/Control Segment.................................................................................................................... 31 Figure 4. Typical Straight Cable Connection ....................................................................................................................... 32 Figure 5. Typical Crossover Cable Connection ................................................................................................................... ...
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Micrel, Inc. List of Tables Table 1. MII Management Frame Format ............................................................................................................................ 25 Table 2. MII Signal Definition ............................................................................................................................................... 26 Table 3. RMII Signal Description.......................................................................................................................................... 28 Table 4. SMII Signal Description.......................................................................................................................................... 29 Table 5. SMII TX Bit Description .......................................................................................................................................... 30 ...
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Micrel, Inc. Pin Configuration – KSZ8041TL GND 2 GND 3 GND 4 VDDA_1.8 5 VDDA_1.8 6 V1.8_OUT 7 VDDA_3.3 8 VDDA_3.3 9 RX- 10 RX+ 11 TX December 2009 ...
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Micrel, Inc. Pin Configuration – KSZ8041FTL GND 2 GND 3 GND 4 VDDA_1.8 5 VDDA_1.8 6 V1.8_OUT 7 VDDA_3.3 8 VDDA_3.3 9 RX- 10 RX+ 11 TX December 2009 ...
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... Management Interface (MII) Clock Input This pin is synchronous to the MDIO data interface. Ipu/O MII Mode: Receive Data Output[3] Config. Mode: The pull-up/pull-down value is latched as PHYADDR[0] during power-up / reset. See “Strapping Options” section for details. Ipd/O MII Mode: Receive Data Output[2] Config. Mode: The pull-up/pull-down value is latched as PHYADDR[1] during power-up / reset. See “ ...
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Micrel, Inc. Pin Number Pin Name 23 RXD0 / RXD[ DUPLEX 24 GND 25 VDDIO_3.3 26 VDDIO_3.3 27 RXDV / CRSDV / CONFIG2 28 RXC 29 RXER / RX_ER / ISO 30 GND 31 VDD_1.8 32 INTRP 33 ...
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Micrel, Inc. Pin Number Pin Name 42 LED0 / (KSZ8041TL) NWAYEN 42 LED0 / (KSZ8041FTL) NWAYEN December 2009 (1) Pin Function Type Ipu/O LED Output: Programmable LED0 Output / Config. Mode: Latched as Auto-Negotiation Enable (register 0h, bit 12) during ...
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Micrel, Inc. Pin Number Pin Name 43 LED1 / (KSZ8041TL) SPEED 43 LED1 / (KSZ8041FTL) SPEED / no FEF December 2009 (1) Pin Function Type Ipu/O LED Output: Programmable LED1 Output / Config. Mode: ...
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... SMII Tx Mode: Transmit data and control information are received in 10 bit segments. In 100MBit mode, each segment represents a new byte of data. In 10MBit mode, each segment is repeated ten times; therefore, every ten segments represent a new byte of data. The PHY can sample any one of every 10 segments in 10MBit mode. ...
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... FEF December 2009 (1) Pin Function Ipd/O The PHY Address is latched at power-up / reset and is configurable to any value from Ipd/O The default PHY Address is 00001. Ipu/O PHY Address bits [4:3] are always set to ‘00’. The CONFIG[2:0] strap-in pins are latched at power-up / reset and are defined as ...
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... Pin strap-ins are latched during power-up or reset. In some systems, the MAC receive input pins may drive high during power-up or reset, and consequently cause the PHY strap-in pins on the MII/RMII/SMII signals to be latched high. In this case recommended to add 1K pull-downs on these PHY strap-in pins to ensure the PHY does not strap-in to ISOLATE mode not configured with an incorrect PHY Address. ...
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Micrel, Inc. Pin Configuration –KSZ8041MLL 1 GND 2 GND 3 GND 4 VDDA_1.8 5 VDDA_1.8 6 V1.8_OUT 7 VDDA_3.3 8 VDDA_3.3 9 RX- 10 RX+ 11 TX- 12 TX+ December 2009 KSZ8041MLL 13 ...
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... Management Interface (MII) Clock Input This pin is synchronous to the MDIO data interface. Ipu/O MII Mode: Receive Data Output[3] Config. Mode: The pull-up/pull-down value is latched as PHYADDR[0] during power-up / reset. See “Strapping Options” section for details. Ipd/O MII Mode: Receive Data Output[2] Config. Mode: The pull-up/pull-down value is latched as PHYADDR[1] during power-up / reset. See “ ...
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Micrel, Inc. Pin Number Pin Name 27 RXDV / CONFIG2 28 RXC 29 RXER / ISO 30 GND 31 VDD_1.8 32 INTRP 33 TXC 34 TXEN 35 TXD0 36 TXD1 37 GND 38 TXD2 39 TXD3 40 COL / CONFIG0 ...
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Micrel, Inc. Pin Number Pin Name 43 LED1 / SPEED RST Notes Power supply. Gnd = Ground Input Output. I/O = Bi-directional. Ipd = ...
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... Pin strap-ins are latched during power-up or reset. In some systems, the MAC receive input pins may drive high during power-up or reset, and consequently cause the PHY strap-in pins on the MII signals to be latched high. In this case recommended to add 1K pull-downs on these PHY strap-in pins to ensure the PHY does not strap-in to ISOLATE mode not configured with an incorrect PHY Address ...
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... PHY status change. Physical signal transmission and reception are enhanced through the use of patented analog circuitries that make the design more efficient and allow for lower power consumption and smaller chip die size. ...
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Micrel, Inc. 10Base-T Receive On the receive side, input buffer and level detecting squelch circuits are employed. A differential input receiver circuit and a PLL performs the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ ...
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Micrel, Inc. Start Auto Negotiation Force Link Setting Yes Bypass Auto Negotiation and Set Link Mode December 2009 N Parallel Operation o Attempt Auto Listen for 100BASE-TX Negotiation Idles Join Flow Link Mode Set ? Yes Link Mode Set Figure ...
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... PHY devices. Each KSZ8041TL/FTL/MLL device is assigned a unique PHY address between 1 and 7 by its PHYAD[2:0] strapping pins. Also, every KSZ8041TL/FTL/MLL device supports the broadcast PHY address 0, as defined per the IEEE 802.3 Specification, which can be used to read/write to a single KSZ8041TL/FTL/MLL device, or write to multiple KSZ8041TL/FTL/MLL devices simultaneously. ...
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... Transmit Data [3:0] (TXD[3:0]) TXD[3:0] transitions synchronously with respect to TXC. When TXEN is asserted, TXD[3:0] are accepted for transmission by the PHY. TXD[3:0] is ”00” to indicate idle when TXEN is de-asserted. Values other than “00” on TXD[3:0] while TXEN is de-asserted are ignored by the PHY. ...
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... PHY. Receive Error (RXER) RXER is asserted for one or more RXC periods to indicate that a Symbol Error (e.g. a coding error that a PHY is capable of detecting, and that may otherwise be undetectable by the MAC sub-layer) was detected somewhere in the frame presently being transferred from the PHY ...
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... RXD[1:0] while CRS_DV is de-asserted are ignored by the MAC. Receive Error (RX_ER) RX_ER is asserted for one or more REF_CLK periods to indicate that a Symbol Error (e.g. a coding error that a PHY is capable of detecting, and that may otherwise be undetectable by the MAC sub-layer) was detected somewhere in the frame presently being transferred from the PHY ...
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... Serial MII (SMII) Data Interface (KSZ8041TL/FTL only) The Serial Media Independent Interface (SMII) is the lowest pin count Media Independent Interface (MII). It provides a common interface between physical layer and MAC layer devices, and has the following key characteristics: x Supports 10Mbps and 100Mbps data rates. ...
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... One Data Byte Receive Data and Control (RX) RX provides receive data and control information from PHY-to-MAC in 10-bit segments 10Mbps mode, each segment is repeated ten times. Therefore, every ten segments represent a new byte of data. The MAC can sample any one of every ten segments. ...
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Micrel, Inc. The following figure and table shows the receive data/control format for each segment: CLOCK SYNC RX CRS RX_DV SMII RX Bit CRS RX_DV RXD[0:7] CRS RX_DV RXD0 RX_ER X 0 from pervious frame X 1 One Data Byte ...
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Micrel, Inc. HP Auto MDI/MDI-X HP Auto MDI/MDI-X configuration eliminates the confusion of whether to use a straight cable or a crossover cable between the KSZ8041TL/FTL/MLL and its link partner. This feature allows the KSZ8041TL/FTL/MLL to use either type of ...
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Micrel, Inc. Crossover Cable A crossover cable connects a MDI device to another MDI device MDI-X device to another MDI-X device. The following diagram depicts a typical crossover cable connection between two switches or hubs (two MDI-X devices). ...
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... Access ® LinkMD is initiated by accessing register 1Dh, the LinkMD PHY Control 2 Register. Usage The following test procedure demonstrates how to use LinkMD 1. Disable auto MDI/MDI-X by writing a ‘1’ to register 1Fh bit 13 to enable manual control over the differential pair used to transmit the LinkMD 2. Select the differential pair to transmit the LinkMD 3. Start cable diagnostic test by writing a ‘ ...
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Micrel, Inc. Reference Clock Connection Options A crystal or clock source, such as an oscillator, is used to provide the reference clock for the KSZ8041TL/FTL/MLL. The following figure illustrates how to connect the 25MHz crystal and oscillator reference clock for ...
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Micrel, Inc. Reference Circuit for Power and Ground Connections The KSZ8041TL/FTL/MLL is a single 3.3V supply device with a built-in 1.8V low noise regulator. The power and ground connections are shown in the following figure and table. Figure 9. KSZ8041TL/FTL/MLL ...
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Micrel, Inc. 100Base-FX Fiber Operation (KSZ8041FTL only) 100Base-FX fiber operation is similar to 100Base-TX copper operation with the differences being that the scrambler/de- scrambler and MLT3 encoder/decoder are bypassed on transmission and reception. In addition, auto-negotiation is bypassed, auto MDI/MDI-X ...
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Micrel, Inc. Back-to-Back Media Converter A KSZ8041TL/MLL and a KSZ8041FTL can be connected back-to-back to provide a low cost media converter solution. In back-to-back mode, media conversion is between 100Base-TX copper and 100Base-FX fiber. On the copper side, link up ...
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Micrel, Inc. RMII Back-to-Back Mode (KSZ8041TL/FTL only) In RMII Back-to-Back mode, the KSZ8041TL interfaces with another KSZ8041TL KSZ8041FTL to provide a complete 100Mbps repeater or media converter solution. The KSZ8041TL/FTL devices are configured to RMII Back-to-Back mode after ...
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... If enabled, auto-negotiation result overrides settings in register 0.13 and 0.8. 0.11 Power Down 1 = Power down mode 0 = Normal operation 0.10 Isolate 1 = Electrical isolation of PHY from MII and 0 = Normal operation 0.9 Restart Auto Restart auto-negotiation process Negotiation 0 = Normal operation. This bit is self-cleared after a ‘1’ is written to it. ...
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... Jabber Detect 1 = Jabber detected 0 = Jabber not detected (default is low) Extended 1 Supports extended capabilities registers Capability Register 2h – PHY Identifier 1 2.15:0 PHY ID Assigned to the 3rd through 18th bits of the Number Organizationally Unique Identifier (OUI). Kendin Communication’s OUI is 0010A1 (hex) December 2009 ...
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... Micrel, Inc. Address Name Description Register 3h – PHY Identifier 2 3.15:10 PHY ID Assigned to the 19th through 24 Number Organizationally Unique Identifier (OUI). Kendin Communication’s OUI is 0010A1 (hex) 3.9:4 Model Number Six bit manufacturer’s model number 3.3:0 Revision Four bit manufacturer’s revision number Number Register 4h – ...
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Micrel, Inc. Address Name Description 5.9 100Base- capable capability 5.8 100Base- 100Mbps full-duplex capable Full-Duplex 100Mbps full-duplex capability 5.7 100Base- 100Mbps half-duplex capable Half-Duplex 0 = ...
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Micrel, Inc. Address Name Description 8.14 Acknowledge 1 = Successful receipt of link word successful receipt of link word 8.13 Message Page 1 = Message page 0 = Unformatted page 8.12 Acknowledge2 1 = Able to act ...
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... Reserved 1d.8:0 Cable Fault Distance to fault; it’s approximately Counter 0.4m*(Cable Fault Counter value in decimal) Register 1Eh – PHY Control 1 1e.15:14 LED mode [00] = [01] = [10], [11] = Reserved 1e.13 Polarity 0 = Polarity is not reversed ...
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... State 1 = MDI-X 1e.10:8 Reserved 1e.7 Remote 0 = Normal mode loopback 1 = Remote (analog) loop back is enable 1e.6:0 Reserved Register 1Fh – PHY Control 2 1f.15 HP_MDIX 0 = Micrel Auto MDI/MDI-X mode Auto MDI/MDI-X mode 1f.14 MDI/MDI-X When Auto MDI/MDI-X is disabled, Select 0 = MDI Mode 1 = MDI-X Mode 1f ...
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... Micrel, Inc. Address Name Description 1f.5 PHY Isolate 1 = PHY in isolate mode 0 = PHY in normal operation 1f.4:2 Operation [000] = still in auto-negotiation Mode [001] = 10Base-T half-duplex Indication [010] = 100Base-TX half-duplex [011] = reserved [101] = 10Base-T full-duplex [110] = 100Base-TX full-duplex [111] = reserved 1f.1 Enable SQE 1 = Enable SQE test ...
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Micrel, Inc. Absolute Maximum Ratings Supply Voltage ( ........................ -0.5V to +2.4V DD_1.8, DDA_1.8, 1.8_OUT ( ................................... -0.5V to +4.0V DDIO_3.3, DDA_3.3 Input Voltage (all inputs) ............................... -0.5V to +4.0V Output Voltage (all outputs) .......................... ...
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... Specification for packaged product only Current consumption is for the single 3.3V supply KSZ8041TL/FTL/MLL device only, and includes the 1.8V supply voltage (V that is provided by the KSZ8041TL/FTL/MLL. The PHY port’s transformer consumes an additional 45mA @ 3.3V for 100Base-TX and 70mA @ 3.3V for 10Base-T. December 2009 ...
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Micrel, Inc. Timing Diagrams MII SQE Timing (10Base-T) TXC TXEN COL Timing Parameter SQE t SQEP December 2009 SQE t SQEP Figure 11. MII SQE Timing ...
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Micrel, Inc. MII Transmit Timing (10Base-T) TXC TXEN t SU2 TXD[3:0] CRS Timing Parameter SU1 t SU2 t HD1 t HD2 t CRS1 t CRS2 December 2009 HD2 t t ...
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Micrel, Inc. MII Receive Timing (10Base-T) Timing Parameter RLAT December 2009 Figure 13. MII Receive Timing (10Base-T) Description RXC period RXC pulse width low RXC pulse width high (RXD[3:0], RXER, RXDV) ...
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Micrel, Inc. MII Transmit Timing (100Base-TX) Timing Parameter SU1 t SU2 t HD1 t HD2 t CRS1 t CRS2 December 2009 Figure 14. MII Transmit Timing (100Base-TX) Description TXC period TXC pulse width ...
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Micrel, Inc. MII Receive Timing (100Base-TX) Timing Parameter RLAT December 2009 Figure 15. MII Receive Timing (100Base-TX) Description RXC period RXC pulse width low RXC pulse width high (RXD[3:0], RXER, RXDV) ...
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Micrel, Inc. RMII Timing Receive Tim ing REFCLK CRSDV RXD[1:0] Timing Parameter t ...
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Micrel, Inc. SMII Timing Timing Parameter December 2009 Figure 18. SMII Timing – Data Received from SMII Figure 19. SMII Timing – Data Input to SMII Description Min Setup time 1.5 Hold time 1.0 ...
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Micrel, Inc. Auto-Negotiation Timing tiatio n F ast ...
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... Timing Parameter Description t MDC period P t MDIO (PHY input) setup to rising edge of MDC 1MD1 t MDIO (PHY input) hold from rising edge of MDC MD2 t MDIO (PHY output) delay from rising edge of MDC MD3 December 2009 MD1 MD2 Valid Data t MD3 Figure 21 ...
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Micrel, Inc. Reset Timing The KSZ8041TL/FTL/MLL reset timing requirement is summarized in the following figure and table. Supply Voltage RST# Strap-In Value Strap-In / Output Pin Parameter After the de-assertion of reset, ...
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Micrel, Inc. Reset Circuit The following reset circuit is recommended for powering up the KSZ8041TL/FTL/MLL if reset is triggered by the power supply. The following reset circuit is recommended for applications where reset is driven by another device (e.g., CPU ...
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Micrel, Inc. The following figure shows the reference circuits for pull-up, float and pull-down on the LED1 and LED0 strapping pins. December 2009 Pull-up KSZ8041TL/FTL/MLL LED pin Float KSZ8041TL/FTL/MLL LED pin Pull-down KSZ8041TL/FTL/MLL LED pin Figure 25. Reference Circuits for ...
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Micrel, Inc. Selection of Isolation Transformer A 1:1 isolation transformer is required at the line interface. An isolation transformer with integrated common-mode chokes is recommended for exceeding FCC requirements. The following table gives recommended transformer characteristics. Parameter Turns ratio Open-circuit ...
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Micrel, Inc. Package Information 48-Pin LQFP December 2009 48-Pin (7mm x 7mm) LQFP Package 63 KSZ8041TL/FTL/MLL M9999-120909-1.2 ...
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Micrel, Inc. 48-Pin TQFP Note: ALL DIMENSIONS ARE IN MILLIMETERS. December 2009 ...
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Micrel, Inc. MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no ...