KSZ8041TL A3 TR Micrel Inc, KSZ8041TL A3 TR Datasheet - Page 29

• Manufacturer Part Number: KSZ8041TL A3 TR
• Manufacturer: Micrel Inc

Specifications of KSZ8041TL A3 TR

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Micrel, Inc.
Collision Detection
The MAC regenerates the COL signal of the MII from TX_EN and CRS_DV.
Serial MII (SMII) Data Interface (KSZ8041TL/FTL only)
The Serial Media Independent Interface (SMII) is the lowest pin count Media Independent Interface (MII). It provides a
common interface between physical layer and MAC layer devices, and has the following key characteristics:
The KSZ8041TL/FTL is configured in SMII mode after it is power-up or reset with the following:
In SMII mode, unused MII signals, TXD[3:2] (pins 39, 38), are tied to ground.
SMII Signal Definition (KSZ8041TL/FTL only)
The following table describes the SMII signals. Refer to SMII Specification for detailed information.
Clock Reference (CLOCK)
CLOCK is sourced by the MAC or system board. It is a continuous 125 MHz clock that provides the timing reference for
SYNC, TX, and RX.
Sync Pulse (SYNC)
SYNC is a 12.5MHz synchronized pulse derived from CLOCK by the MAC. It is used to indicate the segment boundary for
each transmit data/control segment, or receive data/control segment. Each segment is comprised of ten bits.
SYNC is generated continuously by the MAC at every ten cycles of CLOCK.
Transmit Data and Control (TX)
TX provides transmit data and control information from MAC-to-PHY in 10-bit segments.
December 2009
x
x
x
x
x
x
x
x
x
Supports 10Mbps and 100Mbps data rates.
Uses 125MHz reference clock provided by the MAC or the system board.
Uses 12.5MHz sync pulse provided by the MAC.
Provides independent single-bit wide transmit and receive data paths for data and control information.
A 125MHz reference clock connected to CLOCK (pin 15).
A 12.5MHz sync pulse connected to SYNC (pin 36).
CONFIGURATION[2:0] (pins 27, 41, 40) set to ‘010’.
In 10Mbps mode, each segment is repeated ten times. Therefore, every ten segments represent a new byte of
data. The PHY can sample any one of every ten segments.
In 100Mbps mode, each segment represents a new byte of data.
SMII
Signal Name
CLOCK
SYNC
TX
RX
Direction
(with respect to PHY,
KSZ8041TL/FTL signal)
Input
Input
Input
Output
Table 4. SMII Signal Description
Direction
(with respect to MAC)
Input, or Output
Output
Output
Input
29
Description
125 MHz clock reference for receive and
transmit data and control
12.5 MHz sync pulse from MAC
Transmit Data and Control
Receive Data and Control
KSZ8041TL/FTL/MLL
M9999-120909-1.2