FWLXT9784BC.A3 Cortina Systems Inc, FWLXT9784BC.A3 Datasheet
FWLXT9784BC.A3
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FWLXT9784BC.A3 Summary of contents
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... It provides both a Reduced Media Independent Interface (RMII) and a Serial Media Independent Interface (SMII) for switching and other independent port applications. In RMII mode, each PHY has a discrete exposed RMII interface, and in SMII mode a discrete exposed SMII interface. All network ports provide a Twisted-Pair (TP) interface for a 10/100BASE-TX connection ...
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Information in this document is provided in connection with Intel property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express ...
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... BP4B5B (4B/5B Bypass)........................................................................40 2.6.5 SCRMBP (Scrambler Bypass) ...............................................................41 2.7 PHY Addresses ...................................................................................................41 2.8 Link Status Interrupt ............................................................................................41 2.9 Reset ...................................................................................................................42 2.10 LED Operation.....................................................................................................42 2.11 MII Management Interface Operation..................................................................43 2.12 Test Port Operation .............................................................................................44 2.12.1 NAND-Tree Test.....................................................................................44 2.12.2 XNOR-Tree Test ....................................................................................45 Datasheet Low-Power Octal PHY — LXT9784 ....................................................10 ...........................................................................................29 3 ...
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... LXT9784 — Low-Power Octal PHY 2.12.3 NAND/XNOR Tree Chain Order............................................................. 45 3.0 Application Information 3.1 Magnetics............................................................................................................ 48 3.2 Analog References (RBIAS) ............................................................................... 48 3.3 RMII Applications ................................................................................................ 48 3.3.1 RMII Clock.............................................................................................. 49 3.4 SMII Applications ................................................................................................ 49 3.4.1 SMII Clock .............................................................................................. 50 4.0 Test Specifications 4.1 DC Characteristics .............................................................................................. 52 4.2 AC Characteristics .............................................................................................. 53 4.2.1 Common Characteristics ........................................................................ 54 4 ...
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... Figures 1 LXT9784 Block Diagram ....................................................................................... 9 2 LXT9784 Ball Assignments - RMII Mode ............................................................10 3 LXT9784 Ball Assignments - SMII Mode.............................................................11 4 LXT9784 PHY in a 10/100 Mbps Ethernet Solution ............................................29 5 RMII Data Reception ...........................................................................................32 6 False Carrier Detect ............................................................................................32 7 SMII Received Serial Data Stream......................................................................33 8 NRZ to MLT-3 encoding diagram ........................................................................34 9 RMII Data Transmission ...
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... Control Register (Register 0) Bit Definitions ....................................................... 60 44 Status Register (Register 1) Bit Definitions......................................................... 61 45 PHY Identifier Register (Register 2) Bit Definitions ............................................. 62 46 PHY Identifier Register (Register 3) Bit Definitions ............................................. 62 47 Auto-Negotiation Advertisement Register (Register 4) Bit Definitions ................ 62 48 Auto-Negotiation Link Partner Ability Register (Base Page) (Register 5) Bit Definitions .................................................................................. 63 ...
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... Auto-Negotiation Expansion Register (Register 6) Bit Definitions.......................63 50 Register 16 (10 Hex) Status and Control ............................................................64 51 Register 17 (11 Hex) Special Control..................................................................64 52 Register 18 (12 Hex) PHY Interrupt Register ......................................................65 53 Reg 19 (13 Hex) 100 BASE-TX RCV False Carrier Counter ..............................65 54 Reg 20 (14 Hex) 100BASETx Receive Disconnect Counter...............................66 55 Reg 21 (15 Hex) 100BASETx Receive Error Frame Counter ...
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... LXT9784 — Low-Power Octal PHY Revision History Revision Date 8 Description Datasheet ...
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... ID<1:0> Datasheet Digital Equalizer Adaptation Digital Clock 100BASE- Recovery (100) TX PCS Digital Clock 10BASE-T Recovery (10) PCS Auto- Negotiation MII Register Set Low-Power Octal PHY — LXT9784 MODE [2:0] RMII I/F RMII / SMII SMII I/F LEDA Per-Port LEDB LED Drivers LEDC Port ...
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... LXT9784 — Low-Power Octal PHY 1.0 Pin Assignments and Signal Descriptions Figure 2. LXT9784 Ball Assignments - RMII Mode TXD7_1 NC NC TPON7 TPOP7 B CRSDV7 TXEN7 TXD7_0 RXD6_0 RXD7_0 RXD7_1 NC TPIN7 TPIP7 D TXEN6 CRSDV6 RXD6_1 NC GND VCCR E TXD5_1 TXD6_1 TXD6_0 VCCIO GND VCC F CRSDV5 ...
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... VCC RBIAS RBIAS NC TPOP1 TPON1 TPOP2 TPON2 NC 100_0 10_0 Standard input only signal. Standard output-only signal. This is an input and output ball. Low-Power Octal PHY — LXT9784 TPON4 TPOP4 INT MDC TOUT TPIN4 TPIP4 NC LED7_B LED7_A MDIO GND VCCR NC LED6_B LED6_A ...
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... LXT9784 — Low-Power Octal PHY Table 1. Signal Types Type Name OD Open-drain output OZ Tri-state output PU Internal weak pull-up PD Internal weak pull-down Input ball, external pull-down device is not required. EPU External pull up EPD External pull down MLT Multi-level analog I/O A_PWR Power (analog) ...
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... Not Used (SMII TPIN7 C6 TPIP7 TPIN6 C9 TPIP6 C10 GND C11 GND C12 TPIN5 C13 TPIP5 1. Refer to Table 1 on page 11 Datasheet Low-Power Octal PHY — LXT9784 1 Type Reference for Full Description I Table 8 on page Table 9 on page 27 I Table 9 on page Table 6 on page 24 ...
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... LXT9784 — Low-Power Octal PHY Table 2. Numeric Pad Assignments (Continued) Ball Symbol C14 - C15 TPIN4 C16 TPIP4 C17 - C18 LED7_B C19 LED7_A C20 MDIO TXEN6 (RMII) D1 Not Used (SMII) CRSDV6 (RMII) D2 Not Used (SMII) D3 RXD6_1 (RMII) Not Used (SMII GND D6 VCCR ...
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... LED4_A F20 LED5_C RXD4_0 (RMII) G1 RXD4 (SMII) RXD5_0 (RMII) G2 RXD5 (SMII) 1. Refer to Table 1 on page 11 Datasheet Low-Power Octal PHY — LXT9784 1 Type Reference for Full Description O Table 5 on page 23 O Table 5 on page 23 O Table 5 on page 23 O Table 8 on page 26 ...
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... LXT9784 — Low-Power Octal PHY Table 2. Numeric Pad Assignments (Continued) Ball Symbol RXD5_1 (RMII) G3 Not Used (SMII) G4 VCCIO G5 VCC G6 - G16 VCC G17 VCCIO G18 MDI-X G19 LED3_A G20 LED4_C H1 TXEN4 (RMII) NC (SMII) CRSDV4 (RMII (SMII) RXD4_1 (RMII (SMII) H4 GND H5 VCC H16 ...
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... L19 ID_1 L20 ID_0 TXEN3 (RMII) M1 Not Used (SMII) TXD3_0 (RMII) M2 TXD3 (SMII) 1. Refer to Table 1 on page 11 Datasheet Low-Power Octal PHY — LXT9784 1 Type Reference for Full Description NC NC I-PD Table 7 on page 25 I Table 7 on page 25 I Table 7 on page 25 I ...
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... LXT9784 — Low-Power Octal PHY Table 2. Numeric Pad Assignments (Continued) Ball Symbol TXD3_1 (RMII) M3 Not Used (SMII) M4 GND M5 VCC M9 GND M10 GND M11 GND M12 GND M16 VCC M17 GND M18 RXER3 M19 RXER2 M20 RXER1 RXD3_0 (RMII) N1 RXD3 (SMII) RXD3_1 (RMII) ...
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... GND T8 GND T9 VCC T10 GND T11 GND T12 GND 1. Refer to Table 1 on page 11 Datasheet Low-Power Octal PHY — LXT9784 1 Type Reference for Full Description NC O Table 5 on page 23 O Table 5 on page 23 O Table 8 on page 26 I Table 8 on page 26 NC ...
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... LXT9784 — Low-Power Octal PHY Table 2. Numeric Pad Assignments (Continued) Ball Symbol T13 VCC T14 GND T15 GND T16 VCC T17 GND T18 LED1_C T19 LED1_B T20 LED1_A RXD1_0 (RMII) U1 RXD1 (SMII) RXD1_1 (RMII) U2 Not Used (SMII) CRSDV1 (RMII) U3 Not Used (SMII) ...
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... W12 - W13 - W14 - W15 - W16 - W17 - 1. Refer to Table 1 on page 11 Datasheet Low-Power Octal PHY — LXT9784 1 Type Reference for Full Description NC MLT Table 3 on page 22 MLT Table 3 on page 22 NC MLT Table 3 on page 22 MLT Table 3 on page 22 MLT Table 3 on page 22 ...
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... LXT9784 — Low-Power Octal PHY Table 2. Numeric Pad Assignments (Continued) Ball Symbol W18 - W19 - W20 - TPOP0 Y6 TPON0 TPOP1 Y9 TPON1 Y10 RBIAS100_0 Y11 RBIAS10_0 Y12 TPOP2 Y13 TPON2 Y14 - Y15 TPOP3 Y16 TPON3 Y17 - Y18 - Y19 - Y20 - 1. Refer to Table 1 on page 11 Table 3. ...
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... When this signal is not used, a pull-up resistor is required. 1 Type Signal Description Link/Activity LED, Ports 0-7. With a good link the output is Low. The O output blinks at a rate related to the utilization. Table 1 for additional Signal Type Definitions. Low-Power Octal PHY — LXT9784 Signal Description 23 ...
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... LXT9784 — Low-Power Octal PHY Table 5. LED Signal Descriptions (Continued) Ball ID Signal Name U19 LED0_B T19 LED1_B R19 LED2_B P19 LED3_B F18 LED4_B E18 LED5_B D18 LED6_B C18 LED7_B U18 LED0_C T18 LED1_C R18 LED2_C P18 LED3_C G20 LED4_C F20 LED5_C ...
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... Mode of Operation. Sets the LXT9784 mode of operation. See Table 10. ID. Sets the two most significant bits of the PHY addresses. I-PD The ID<1:0> pins are used to set the PHY addresses for accessing the PHY registers through the MII management interface. OD Link Status Interrupt. The Link status change interrupt line. ...
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... LXT9784 — Low-Power Octal PHY Table 8. RMII Mode Signal Descriptions Ball ID V1 CRSDV0 U3 CRSDV1 P1 CRSDV2 N3 CRSDV3 H2 CRSDV4 F1 CRSDV5 D2 CRSDV6 B1 CRSDV7 L18 RXER0 M20 RXER1 M19 RXER2 M18 RXER3 N20 RXER4 N19 RXER5 N18 RXER6 P20 RXER7 V2, V3 RXD0_1, RXD0_0 U2, U1 RXD1_1, RXD1_0 ...
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... Transmit Data and Control, Ports 0-7. Transmit data stream, that contains all of the information found on the transmit path I of the standard MII. I Synchronization. Defines the SMII segment boundaries. for Signal Type Definitions. Low-Power Octal PHY — LXT9784 Signal Description Signal Description 27 ...
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... LXT9784 — Low-Power Octal PHY Table 10. Unused Pins A1,A3,A4,A7,A14,A17,A18,A,19,A20, B4,B5,B6,B7,B8,B9,B12,B13,B14,B15, B16,B17,C4,C7,C14,C17,D4,D7,D14, D17,F5,F6,F14,F15,F16,G6,J18,J19,J20, P15,R5,R6,R7,R15,R16,U4,U7,U14,U17,V4, V7, V14, V17,V18,V19,V20,W4,W5,W6, W7,W8,W9,W12,W13,W14,W15,W16, W17,W18,W19,W20,Y1,Y2,Y3,Y4,Y7, Y14,Y17,Y18,Y19,Y20. A1,A2,A3,A4,A7,A14,A17,A18,A,19, A20,B1,B2,B4,B5,B6,B7,B8,B9,B12,B13, B14,B15,B16,B17,C3,C4,C7,C14,C17, D1,D2,D3,D4,D7,D14,D17,E1,E2,F1,F2, F5,F6,F14,F15,F16,G3,G6,J2,J18,J19,J20,L18,M1,M 3,N2,N3,N18,N19,N20,P1,P2, P15,R1,R3,R5,R6,R7,R15,R16,T1,T3,U2,U4,U7,U14, U17,V1,V2,V4,V7, V14, V17,V18,V19,V20,W1,W3,W4,W5,W6,W7, W8, W9,W12,W13,W14,W15,W16, W17,W18,W19,W20,Y1,Y2,Y3,Y4,Y7, Y14,Y17,Y18,Y19,Y20. 28 Ball ID Symbol NC NC Type Description No Connection- These pins RMII are not used in RMII mode ...
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... LXT9784 Configuration The LXT9784 has a common Management Data Interface (MDI) for the eight PHYs. This is a serial interface and complies with the IEEE 802.3Standard MII for MDC and MDIO signals. In all modes of operation the PHYs can be configured individually using the MII management interface. ...
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... Each receive subsection of the LXT9784 PHYs accepts 100BASE-TX MLT-3 data on TPIPn and TPINn (where “n” is the port number). Due to the advanced digital signal processing design techniques employed, the PHYs accurately receive valid data from CAT5 UTP and type 1 STP cable over distances well in excess of 100 meters. ...
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... Decoder The LXT9784 PHYs first convert the data from the clock recovery circuitry to NRZ format. The NRZ serial data stream is assembled to 5-bit symbols, de-scrambled and aligned to symbol boundaries. The de-scrambling is based on synchronization to the transmitted Idle pattern generated by an 11-bit LFSR during idle. The data is then decoded at the 5B/4B decoder. ...
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... LXT9784 — Low-Power Octal PHY 2.3.1.8 100BASE-TX Receive Error Detection and Reporting In 100BASE-TX mode, the PHYs detect errors in the receive data in a number of ways. Any of the following conditions is considered an error: • If the SSD ("JK") symbol is not fully detected after idle • ...
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... RXD0 2.3.2 100BASE-TX Transmitter The transmit subsection of the LXT9784 PHY device accepts di-bit data on TXDn_[1:0] (RMII interface) or serial stream data on TXDn (SMII interface) while TXENn is asserted (High). The data is assembled into nibbles and passed to the 4B/5B encoder as long as TXENn is active. The 4B/5B encoder compiles the data into 5-bit-wide parallel symbols. These symbols are ...
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... LXT9784 — Low-Power Octal PHY Figure 8. NRZ to MLT-3 encoding diagram Table 13. 4B/5B Coding Code Type DATA IDLE undefined CONTROL undefined undefined undefined undefined 1. The /I/ (Idle) code group is sent continuously between frames. 2. The /J/ and /K/ (SSD) code groups are always sent in pairs; /K/ follows /J/. ...
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... TXDn_[1:0] lines, or serial stream data on the SMII TXDn line. The PHY encodes the data, and sends it out onto the wire. The PHY substitutes the first byte of the preamble with the "JK" symbol pair, encodes all other pieces of data according to the 4B/5B lookup table, and adds the " ...
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... SYNC pulse (every 10 clocks). When TX_EN in the serial bit stream is de-asserted, then TXD[7:0] are the inter-frame control bits (for a direct MAC to MAC connection). When the TX_EN bit asserts, the PHY accepts the data stream on the TXDn line. Figure 10. SMII Transmit Data Serial Stream ...
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... PHY uses parallel detection of the respective technology. For fast link pulses, the PHY uses auto-negotiation. The 10BASE-T link pulses or NLPs are driven on the TPOn line. The link beat pulse is also used to determine if the receive pair polarity is reversed ...
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... TPOPn and TPONn pins and by externally sharing the same magnetics Mbps mode, the LXT9784 PHYs begin transmitting the serial Manchester bit stream within 3 bit times (300 ns) after the assertion TXENn. In 10-Mbps mode the line drivers use a pre-distortion algorithm to improve jitter tolerance. The line drivers reduce their drive level during the second half of “ ...
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... In the case that auto-switching was enabled during reset, the PHY attempts to detect link activity in a given configuration (MDI or MDI-X) for a duration 100 ms link activity is detected during this slot time, the PHY waits a random amount of time greater then 80 ms, and switches the MDI pairs to the other configuration. ...
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... FRCLNK (Force Link) During RESET: • When FRCLNK = 1, it forces good link (PHY reg17, bit 11), link integrity (PHY reg17, bit 1), and disables auto-negotiation (PHY reg0, bit 12) • When FRCLNK = 0, Normal Operation. If FRCLNK was set, then after reset the FRCLNK pin will control speed selection (PHY reg0, bit 13), where: • ...
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... When INT is driven low, all of the PHY interrupt registers should be read, to determine which port or ports caused the interrupt (Refer to Table 51). Once a PHY interrupt bit has been read self- cleared. The interrupt line becomes inactive only after reading the Link Status Interrupt bits of all the PHYs that caused the interrupt. In the case of more than one PHY having an interrupt pending, INT remains asserted until after reading the last PHY with a Link Status Interrupt bit set to “ ...
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... In case the port is disabled, register 0. drivers LEDn_A and LEDn_B blink in unison rate of 1 Hz, 500 ms on and 500 ms off. Eliminate the indication of PHY port disable by setting the PHY register 1B’h, bit 4. There is full controllability on all drivers through PHY register 1B’h, bits [2:0] ...
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... MDC and the LXT9784 latches that data on the rising edge of MDC. The PHY addresses in the LXT9784 can be configured from 0-31. The management frame structure is shown in This structure allows a controller or other management hardware, to query a PHY for status of the link, auto-negotiation registers, or configure the PHY to one of many modes. protocol terms. ...
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... During a read transaction the PHY should not drive MDIO in the first bit time and the drive a zero in the second bit time. During a write transaction a "10" pattern is driven to PHY. 16 bits of data driven by the PHY on read transaction, and will be driven to PHY on write Data transaction ...
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... The following table lists the chains order / direction (pin no the chain, is the farthest from the NAND-TREE / XNOR-TREE outputs).] Table 22. Test Scan Chain Chain Order Datasheet Ball ID Chain #1 W1 TXD0_1 W2 TXD0_1 W3 TXEN0 V1 CRSDV0 V2 RXD0_1 Low-Power Octal PHY — LXT9784 Ball ID Chain #2 W18 NC W19 NC W20 NC V18 NC V19 NC 45 ...
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... LXT9784 — Low-Power Octal PHY Table 22. Test Scan Chain (Continued) Chain Order Ball ID Chain #1 V3 RXD0_0 U1 RXD1_0 U2 RXD1_1 U3 CRSDV1 T1 TXEN1 T2 TXD1_0 T3 TXD1_1 R1 TXD2_1 R2 TXD2_0 R3 TXEN2 P1 CRSDV2 P2 RXD2_1 P3 RXD2_0 N1 RXD3_0 N2 RXD3_1 N3 CRSDV3 M1 TXEN3 M2 TXD3_0 M3 TXD3_1 L1 TXD4 L3 FRC34 K3 MCLK K1 FRCLNK J2 TXD4_1 J3 TXD4_0 H1 TXEN4 ...
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... Chain Order NAND-TREE / XNOR-TREE Output Datasheet Ball ID Chain #1 D2 CRSDV6 D3 RXD6_1 C1 RXD6_0 C2 RXD7_0 C3 RXD7_1 B1 CRSDV7 B2 TXEN7 B3 TXD7_0 A2 TXD7_1 B18 INT# Low-Power Octal PHY — LXT9784 Ball ID Chain #2 D19 LED6_A# D20 LED7_C# C18 LED7_B# C19 LED7_A# C20 MDIO B19 MDC - - - - - - B20 TOUT 47 ...
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... See Figure 12. Typical RBIAS Circuit 3.3 RMII Applications The RMII ports provide eight low pin-count interfaces between the eight PHYs and an ASIC switch alternative to the SMII interface. The RMII interface is composed of seven signals per port, and a global reference clock. 48 ...
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... ID[1:0] 3.4 SMII Applications The SMII ports provide eight low pin-count interfaces between the LXT9784’s eight PHYs and an ASIC switch alternative to the RMII interface. The SMII interface is composed of two signals per port, a global synchronization signal, and a global reference clock. Datasheet Low-Power Octal PHY — ...
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... LXT9784 — Low-Power Octal PHY Data and control bits are transmitted and received serially synchronous to MCLK, in ten bit segments delimited by a pulse on SYNC, on RXDn and TXDn respectively. 3.4.1 SMII Clock In SMII mode of operation, the master input clock (MCLK) frequency should be 125 MHz, ± ...
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... CC Vcc 3.15 3.45 - 680 /750 775 - 635 / 680 - 715 / 800 850 - 710 / 760 - - - 334 367 1.0 Low-Power Octal PHY — LXT9784 represent the performance Table 41 are guaranteed over the Maximum Units 100 o -40 + 100 120 o -40 + 120 + Units Condition ...
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... V Output High Voltage V Input Leakage Current I ILIH Input Capacitance C 1. “General Interface” refers to the following: MII management, configuration and PHY ID. 2. Characterized, not tested. Valid for digital pins only. Table 28. LED DC Characteristics Parameter Symbol Output Low Voltage V OLLED Output High Voltage ...
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... AC Characteristics Figure 15 defines the conditions under which timing measurements are done. The design must guarantee proper operation for voltage swings and slew rates that exceed the specified test conditions. Datasheet Low-Power Octal PHY — LXT9784 Symbol Min Typ Max V 2.2 2 ...
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... LXT9784 — Low-Power Octal PHY Figure 15. AC Testing Level Conditions 4.2.1 Common Characteristics Figure 16. MDC Clock AC Timing 1.4v Table 33. MII Management Clock Specifications Parameter MDC Frequency MDC clock period MDC duty cycle Figure 17. MII Management Timing Parameters: MDC/MDIO MDC MDIO (Input) ...
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... Min Typ Max T6 100 T10 T8 Data Pulse T13 T12 Symbol Min Typ T8 100 T9 111 125 T10 55.5 62.5 Low-Power Octal PHY — LXT9784 Max Units Condition ns ns 200 ns Units Condition ns 10 Mbps ms 10 Mbps Clock Pulse Max Units Condition ns 139 s 69 ...
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... LXT9784 — Low-Power Octal PHY Table 36. Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters Parameter Number of pulses in one burst Burst width FLP Burst period Table 37. 100BASE-TX Transmitter AC Specifications Parameter TPOP/TPON Differential Output Peak Jitter 4.3 RMII Interface Figure 20. RMII AC Testing Level Conditions 1 ...
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... Data Valid Previous Data Valid Symbol Min T54 ( RMSU T55 ( RMHD T56 ( RMVLM T56a (T ) RMVLX T57 ( RMFR 1.4V 2.0V 0.8V Low-Power Octal PHY — LXT9784 T55 Data Invalid T56 T56a Data Data Valid Invalid Typ Max Units Condition 1.4V 2.0V 0.8V 57 ...
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... LXT9784 — Low-Power Octal PHY Figure 24. SMII Timing Parameters MCLK TXD Input Output RXD Table 39. SMII Interface Timing Parameters Parameter TXD setup to MCLK rising edge TXD hold from MCLK rising edge RXD min. Valid time RXD max. Valid time 4.5 Reset Timing Parameters Figure 25 ...
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... The MCLK frequency shall be ±50 PPM. 2. Trace characteristic impedance (Z ), 60W ±10%. 0 Datasheet T60 T60 T61 T62 T62 Symbol Min Typ Max ) 35 MCLK_DC ) 20 MCLK_PR ) 8 MCLK_PR ) 3 MCLK_SL ) MCLK_JIT Low-Power Octal PHY — LXT9784 Table 41 defines the Units Condition RMII Mode - 50 MHz ns SMII Mode - 125 MHz V/ns 100 ps Peak 59 ...
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... Table 43. Control Register (Register 0) Bit Definitions Bit(s) Name Sets the status and control register of the PHY to their default states and is self- clearing. The PHY returns a value of “1” when this register is read until the reset process has completed and accepts a read or write transaction. ...
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... Controls the duplex mode when auto-negotiation is disabled. If the PHY reports that it only able to operate in one duplex mode (via bits 1.15:11), the value of this bit shall correspond to the mode which the PHY can operate. When the PHY is placed in Loopback mode, the behavior of the PHY shall not be 0.8 Duplex Mode affected by the status of this bit, bit 0 ...
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... LXT9784 — Low-Power Octal PHY Table 45. PHY Identifier Register (Register 2) Bit Definitions Bit(s) Name 2.15:0 PHY ID (word MSB Read Only. Table 46. PHY Identifier Register (Register 3) Bit Definitions Bit(s) Name 3.15:0 PHY ID (word LSB Read Only. Table 47. Auto-Negotiation Advertisement Register (Register 4) Bit Definitions ...
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... Bit Definitions Bit(s) Name 5.15 Next Page Reflects the PHY’s link partner’s Auto-Negotiation ability Indicates that the PHY has successfully received its link partner’s Auto- 5.14 Acknowledge Negotiation advertising ability. 5.13 Remote Fault Reflects the PHY’s link partner’s Auto-Negotiation ability. ...
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... Indicates the power state of 10BASE-T. 1= Power-Down. 0= Normal operation. Indicates 10BASE-T polarity Reverse polarity normal polarity. Must be set to zero during write. Value determined by ID[1:0] and PHY port number (which of 8) Indicates the Auto-Negotiation result 100 Mbps Mbps. Indicates the Auto-Negotiation result Full Duplex Half Duplex. ...
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... Bit(s) Name 18.15:2 Reserved Constant “0”. Enables the assertion of a specific PHY Interrupt line. However, bit 0 is not masked, and the interrupt bit will remain visible. 18.1 Interrupt Enable 1 = enable the assertion of the interrupt line. default 0 = disable the interrupt line. ...
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... LXT9784 — Low-Power Octal PHY Table 54. Reg 20 (14 Hex) 100BASETx Receive Disconnect Counter Bit(s) Name A 16 bit counter that increments for each disconnect event. The counter stops when Disconnect full (and does not roll over). Self clears on read. 20[15:0] Event Two or more consecutive False carrier events causes this counter to increment. ...
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... Name 27.15:5 Reserved Constant “0” LED blink disabled. 27.4 LED Blink default 0 = LED blink enabled (normal operation). Enables carrier sense disconnection while PHY in jabber at 100Mbps. 100RX Jabber 27 Carrier sense disconnection enabled. Enable default 0 = Carrier sense disconnection disabled. [2:0] LEDA 000 ...
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... LXT9784 — Low-Power Octal PHY 6.0 Mechanical Specifications Figure 28. Package Specifications 68 Parameter N Ball Count A Overall Height A Stand Off 1 A Encapsulation Height 2 D Package Body Length D Encapsulant Length 1 Outer Ball Center to Edge Body B Ball Diameter C Substrate Thickness .32/.52 (2L/4L) E Ball Pitch 1. All dimensions in millimeters ...