FWLXT9784BC.A3 Cortina Systems Inc, FWLXT9784BC.A3 Datasheet - Page 35

• Manufacturer Part Number: FWLXT9784BC.A3
• Manufacturer: Cortina Systems Inc

Specifications of FWLXT9784BC.A3

• Lead Free Status / RoHS Status: Not Compliant

2.3.2.3
2.3.2.4
Datasheet
Table 13. 4B/5B Coding (Continued)
Transmit Driver
The TPOPn and TPONn lines are implemented with a highly slope-controlled driver that meets the
TP-PMD specifications. The driver either sinks, floats, or drives the TPOPn and TPONn outputs
with 20 ma of current, depending on whether the ternary signal is -1, 0, or +1. The magnetics
external to the LXT9784 converts this current to voltage levels of 2.0 Vptp, as required by the TP-
PMD specification.
There are four inputs (RBIAS10_0, RBIAS10_1, and RBIAS100_0, RBIAS100_1) to the
LXT9784 that must have external resistor connections to set up voltage biases for the internal
analog section of the LXT9784 PHYs. RBIAS10_0 and RBIAS100_0 provide the bias for PHYs 0
through 3. RBIAS10_1 and RBIAS100_1 provide the bias for PHYs 4 through 7.
100BASE-TX Transmit Framing
The LXT9784 PHYs do not differentiate between the fields of the MAC frame containing
preamble, SFD, data and CRC. When TXENn is asserted, the PHY accepts di-bit data on the RMII
TXDn_[1:0] lines, or serial stream data on the SMII TXDn line.
The PHY encodes the data, and sends it out onto the wire. The PHY substitutes the first byte of the
preamble with the "JK" symbol pair, encodes all other pieces of data according to the 4B/5B
lookup table, and adds the "TR" code after the end of the packet (de-assertion of TXENn transmit
enable indication). The PHY scrambles and serializes the data into a 125 Mbps stream, encodes it
as MLT-3, and drives it onto the wire. If TXER bit in the SMII control word is asserted while
TXENn bit is active, the LXT9784 transmits an invalid "H" symbol.
100BASE-TX RMII Data Transmission
When TXENn is de-asserted, the data on TXDn_[1:0] shall be "00" to indicate idle. When TXENn
asserts, the PHY accepts di-bit data on the TXDn_[1:0] lines. See
1. The /I/ (Idle) code group is sent continuously between frames.
2. The /J/ and /K/ (SSD) code groups are always sent in pairs; /K/ follows /J/.
3. The /T/ and /R/ (ESD) code groups are always sent in pairs; /R/ follows /T/.
4. An /H/ (Error) code group is used to signal an error condition.
Code Type
INVALID
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4B Code
3 2 1 0
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Name
5B Code
4 3 2 1 0
0 0 0 0 1
0 0 0 1 0
0 0 0 1 1
0 0 1 0 1
0 1 0 0 0
0 1 1 0 0
0 1 1 0 0
1 0 0 0 0
1 1 0 0 1
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Low-Power Octal PHY — LXT9784
Figure
Interpretation
9.
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