KS8737 Micrel Inc, KS8737 Datasheet - Page 10

• Manufacturer Part Number: KS8737
• Manufacturer: Micrel Inc

Specifications of KS8737

• Lead Free Status / RoHS Status: Not Compliant

KS8737
Auto-Negotiation
The KS8737 performs auto-negotiation by hardware (mode[1:0]) or software (Register 0.12). It will automatically choose its
mode of operation by advertising its abilities and comparing them with those received from its link partner whenever auto-
negotiation is enabled. It can also be configured to advertise 100BaseTX or 10BaseT in either full- or half-duplex mode. The
auto-negotiation is disabled in the FX mode.
During auto-negotiation, the contents of Register 4, coded in Fast Link Pulse (FLP), will be sent to its link partner under the
conditions of power-on, link-loss or re-start. At the same time, the KS8737 will monitor incoming data to determine its mode
of operation. Parallel detection circuit will be enabled as soon as either 10BaseT idle or 100BaseTX idle is detected. The
operation mode gets configured based on the following priority:
When the KS8737 receives a burst of FLP from its link partner with 3 identical link code words (ignoring acknowledge bit), it
will store these code words in Register 5 and wait for the next 3 identical code words. Once the KS8737 detects the second
code words, it then configures itself according to above-mentioned priority. In addition, the KS8737 also checks 100BaseTX
idle or 10BaseT NLP symbol. If either is detected, the KS8737 automatically configures to match the detected operating speed.
MII Management Interface
The KS8737 supports the IEEE 802.3 MII Management Interface, also known as the Management Data Input / Output (MDIO)
Interface. This interface allows upper-layer devices to monitor and control the state of the KS8737. The MDIO interface consists
of the following:
The INTPRT pin functions as a management data interrupt in the MII. An active Low or High in this pin indicates a status change
on the KS8737 based on 1fh.14 level control. Register 1bh[15:8] are the interrupt enable bits. Register 1bh[7:0] are the interrupt
conditions bits. The interrupt is activated when changes made to the following conditions:
Reading Register 1bh clears this interrupt.
MII Data Interface
The data interface consists of separate channels for transmitting data from a 10/100 802.3 compliant Media Access Controller
(MAC) to the KS8737, and for receiving data from the line. Normal data transmission is implemented in 4B Nibble Mode (4-
bit wide nibbles).
Transmit Clock (TXC): The transmit clock is normally generated by the KS8737 from an external 25MHz reference source
at the X1 input. The transmit data and control signals must always be synchronized to the TXC by the MAC. The KS8737
normally samples these signals on the rising edge of the TXC.
Receive Clock (RXC): For 100BaseTX links, the receive clock is continuously recovered from the line. If the link goes down,
and auto-negotiation is disabled, receive clock operates off the master input clock (X1 or TXC). For 10BaseT links, received
is recovered from the line while carrier is active, and operates from the master input clock when the line is idled. The KS8737
synchronizes the receive data and control signals on the falling edge of RXC in order to stabilize the signals at the rising edge
of the clock with 10ns setup and hold times.
Transmit Enable: The MAC must assert TXEN the same time as the first nibble of preamble, and de-assert TXEN after the
last bit of the packet.
Receive Data Valid: The KS8737 asserts RXDV when it receives a valid packet. Line operating speed and MII mode will
determine timing changes in the following way:
KS8737
• A physical connection including a data line (MDIO), a clock line (MDC) and an optional interrupt line (INTRPT)
• A specific protocol which runs across the above-mentioned physical connection and allows one controller to
• An internal addressable set of fourteen 16-bit MDIO registers. Register [0:6] are required and their functions are
• Link Status
• Duplex Status
• For 100BaseTX link with the MII in 4B mode, RXDV is asserted from the first nibble of preamble to the last nibble
• For 10BaseT links, the entire preamble is truncated. RXDV is asserted with the first nibble of the SFD “ 5D” and
Priority 1: 100BaseTX, Full-duplex
Priority 2: 100BaseTX, Half-duplex
Priority 3: 10BaseT, Full-duplex
Priority 4: 10BaseT, Half-duplex
communicate with multiple KS8737 devices. Each KS8737 assigned an MII address between 0 and 31 by the
PHYAD inputs.
specified by the IEEE 802.3 specifications. Additional registers are provided for expanded functionality.
of the data packet.
remains asserted until the end of the packet.
10
August 2003
Micrel