XC5VLX50T-1FFG665C Xilinx Inc, XC5VLX50T-1FFG665C Datasheet - Page 62

FPGA, VIRTEX-5 LXT, 50K, 665FCBGA

XC5VLX50T-1FFG665C

Manufacturer Part Number
XC5VLX50T-1FFG665C
Description
FPGA, VIRTEX-5 LXT, 50K, 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG665C

No. Of Logic Blocks
7200
Family Type
Virtex-5
No. Of Speed Grades
1
Total Ram Bits
2211840
No. Of I/o's
360
Clock Management
DCM, PLL
I/o Supply Voltage
3.3V
Operating Frequency Max
550MHz
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
Core Supply Voltage Range
1V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
122-1565

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Bonase Electronics (HK) Co., Limited Bonase Electronics (HK) Co., Limited
Part Number:
XC5VLX50T-1FFG665C4060
Manufacturer:
XILINX
Quantity:
1 122
Price:
Virtex-5 Device Pin-to-Pin Output Parameter Guidelines
All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are
listed in
Table 84: Global Clock Input to Output Delay Without DCM or PLL
DS202 (v5.3) May 5, 2010
Product Specification
Notes:
1.
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, without DCM or PLL
T
ICKOF
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
Symbol
Table
84. Values are expressed in nanoseconds unless otherwise noted.
Global Clock and OUTFF without DCM or PLL
Description
www.xilinx.com
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
XC5VLX20T
XC5VLX30
XC5VLX30T
XC5VLX50
XC5VLX50T
XC5VLX85
XC5VLX85T
XC5VLX110
XC5VLX110T
XC5VLX155
XC5VLX155T
XC5VLX220
XC5VLX220T
XC5VLX330
XC5VLX330T
XC5VSX35T
XC5VSX50T
XC5VSX95T
XC5VSX240T
XC5VTX150T
XC5VTX240T
XC5VFX30T
XC5VFX70T
XC5VFX100T
XC5VFX130T
XC5VFX200T
Device
5.54
5.54
5.59
5.59
5.78
5.78
5.84
5.84
6.16
6.16
5.72
5.77
5.73
5.82
6.21
6.28
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
-3
Speed Grade
5.98
6.04
6.04
6.09
6.09
6.28
6.28
6.35
6.35
6.68
6.68
6.99
6.99
7.17
7.17
6.22
6.27
6.59
7.24
6.58
6.88
6.21
6.33
6.73
6.80
7.17
-2
6.69
6.73
6.73
6.79
6.79
6.99
6.99
7.06
7.06
7.52
7.52
7.71
7.71
7.91
7.91
6.92
6.97
7.30
7.98
7.30
7.61
6.89
7.04
7.44
7.52
7.91
-1
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
62

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