PIC12F1840-I/P Microchip Technology, PIC12F1840-I/P Datasheet - Page 187
![7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core 8 PDI](/photos/16/3/160349/pdip8_sml.jpg)
PIC12F1840-I/P
Manufacturer Part Number
PIC12F1840-I/P
Description
7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core 8 PDI
Manufacturer
Microchip Technology
Datasheet
1.PIC12F1840-IP.pdf
(382 pages)
Specifications of PIC12F1840-I/P
Processor Series
PIC12F
Core
PIC
Program Memory Type
Flash
Program Memory Size
7 KB
Data Ram Size
256 B
Interface Type
MI2C, SPI, EUSART
Number Of Timers
3
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Package / Case
PDIP-8
Development Tools By Supplier
MPLAB IDE Software
Minimum Operating Temperature
- 40 C
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC12F1840-I/P
Manufacturer:
MICROCHIP
Quantity:
200
- Current page: 187 of 382
- Download datasheet (4Mb)
REGISTER 23-4:
TABLE 23-1:
2011 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7
bit 6
bit 5
bit 4
bit 3-0
Note 1:
Name
MDCARH
MDCARL
MDCON
MDSRC
Legend:
MDCLODIS
R/W-x/u
Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized.
MDMSODIS
— = unimplemented, read as ‘0’. Shaded cells are not used in the Data Signal Modulator mode.
MDCHODIS
MDCLODIS
MDEN
Bit 7
MDCLODIS: Modulator Low Carrier Output Disable bit
1 = Output signal driving the peripheral output pin (selected by MDCL<3:0> of the MDCARL register)
0 = Output signal driving the peripheral output pin (selected by MDCL<3:0> of the MDCARL register)
MDCLPOL: Modulator Low Carrier Polarity Select bit
1 = Selected low carrier signal is inverted
0 = Selected low carrier signal is not inverted
MDCLSYNC: Modulator Low Carrier Synchronization Enable bit
1 = Modulator waits for a falling edge on the low time carrier signal before allowing a switch to the high
0 = Modulator Output is not synchronized to the low time carrier signal
Unimplemented: Read as ‘0’
MDCL<3:0> Modulator Data High Carrier Selection bits
1111 = Reserved. No channel connected.
0101 = Reserved. No channel connected.
0100 = CCP1 output (PWM Output mode only)
0011 = Reference Clock module signal
0010 = Reserved. No channel connected.
0001 = MDCIN1 port pin
0000 = V
MDCLPOL
SUMMARY OF REGISTERS ASSOCIATED WITH DATA SIGNAL MODULATOR MODE
R/W-x/u
is disabled
is enabled
time carrier
•
•
•
MDCARL: MODULATION LOW CARRIER CONTROL REGISTER
MDCHPOL
MDCLPOL
SS
MDOE
Bit 6
—
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
MDCLSYNC
R/W-x/u
MDCHSYNC
MDCLSYNC
MDSLR
Bit 5
—
U-0
Preliminary
—
MDOPOL
Bit 4
—
—
—
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
R/W-x/u
MDOUT
Bit 3
(1)
Bit 2
R/W-x/u
—
MDCH<3:0>
MDMS<3:0>
MDCL<3:0>
PIC12(L)F1840
MDCL<3:0>
(1)
Bit 1
—
R/W-x/u
MDBIT
DS41441B-page 187
Bit 0
R/W-x/u
Register
on Page
186
187
184
185
bit 0
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