PIC16F1828-E/SO Microchip Technology, PIC16F1828-E/SO Datasheet - Page 3
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PIC16F1828-E/SO
Manufacturer Part Number
PIC16F1828-E/SO
Description
7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 18 I/0, Enhanced Mid Range Core 20 S
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheets
1.PIC16F722-ISS.pdf
(8 pages)
2.PIC16F1824-ISL.pdf
(2 pages)
3.PIC16F1824-ISL.pdf
(419 pages)
4.PIC16F1824-ISL.pdf
(10 pages)
Specifications of PIC16F1828-E/SO
Core Processor
PIC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-SOIC (0.300", 7.50mm Width)
Processor Series
PIC16F
Core
PIC
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Silicon Errata Issues
1. Module: ADC
1.1 Analog-to-Digital Conversion
1.
2.
FIGURE 1:
2010 Microchip Technology Inc.
Note:
See the ADC Clock Period (T
section of the data sheet.
F
T
T
An ADC conversion may not complete under these
conditions:
When F
clock source used for the ADC converter.
The ADC is operating from its dedicated internal
FRC oscillator and the device is not in Sleep
mode (any F
When this occurs, the ADC Interrupt Flag (ADIF)
does not get set, the GO/DONE bit does not get
cleared, and the conversion result does not get
loaded into the ADRESH and ADRESL result
registers.
CY
AD
OSC
= 4/32 MHz = 125 nsec
= 1 µsec, ADCS = F
= 32 MHz
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A3).
4 T
OSC
8 T
1 T
CY
CY
is greater than 8 MHz and it is the
OSC
AD
INSTRUCTION CYCLE DELAY CALCULATION EXAMPLE
frequency).
OSC
/32
AD
) vs. Device Operating Frequencies table, in the Analog-to-Digital Converter
88 T
11 T
84 T
CY
AD
CY
PIC16(L)F1824/1828
Work around
Method 1: Select the system clock, F
Method 2: Select
Method 3: This method is provided if the
the ADC clock source and reduce
the F
less
conversions.
oscillator as the ADC conversion
clock source and perform all
conversions with the device in
Sleep.
application cannot use Sleep
mode and requires continuous
operation at frequencies above 8
MHz. This method requires early
termination of an ADC conver-
sion. Provide a fixed time delay in
software to stop the A-to-D
conversion manually, after all 10
bits are converted, but before the
conversion would complete auto-
matically.
stopped by clearing the GO/
DONE bit in software. The GO/
DONE bit must be cleared during
the last ½ T
conversion would have com-
pleted automatically. Refer to
Figure 1
Stop the A/D conversion
between 10.5 and 11 T
cycles.
See the Analog-to-Digital
Conversion
figure in the Analog-to-
Digital Converter section of
the data sheet.
OSC
when
for details.
the
frequency to 8 MHz or
The
AD
performing
dedicated
cycle, before the
T
DS80510C-page 3
AD
conversion
Cycles
AD
OSC
ADC
FRC
, as
is