PIC16F1829-E/SO Microchip Technology, PIC16F1829-E/SO Datasheet - Page 253

• Manufacturer Part Number: PIC16F1829-E/SO
• Description: 14 KB Flash, 1K Bytes RAM, 32 MHz Int. Osc, 18 I/0, Enhanced Mid Range Core 20 S
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ mTouch™ 16Fr

Specifications of PIC16F1829-E/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: *
• Processor Series: PIC16F182x
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 5
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

25.2.6
In SPI Master mode, module clocks may be operating
at a different speed than when in full power mode; in
the case of the Sleep mode, all clocks are halted.
Special care must be taken by the user when the
MSSPx clock is much faster than the system clock.
In Slave mode, when MSSPx interrupts are enabled,
after the master completes sending data, an MSSPx
interrupt will wake the controller from Sleep.
If an exit from Sleep mode is not desired, MSSPx inter-
rupts should be disabled.
TABLE 25-1:
 2010 Microchip Technology Inc.
ANSELA
ANSELB
ANSELC
APFCON0
APFCON1
INLVLA
INLVLB
INLVLC
INTCON
PIE1
PIR1
SSP1BUF
SSP1CON1
SSP1CON3
SSP1STAT
TRISA
TRISB
TRISC
Legend:
Note
Name
(1)
(1)
1:
2:
(1)
*
SPI OPERATION IN SLEEP MODE
— = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP1 in SPI mode.
Page provides register information.
PIC16F/LF1829 only.
PIC16F/LF1825 only.
Synchronous Serial Port Receive Buffer/Transmit Register
INLVLC7
RXDTSEL
TMR1GIE
TRISC7
ANSC7
TMR1GIF
INLVLB7
ACKTIM
TRISB7
ANSB7
WCOL
Bit 7
SMP
GIE
—
—
—
—
SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION
(1)
(1)
(1)
SDOSEL
INLVLC6
TRISC6
ANSC6
INLVLB6
SSPOV
TRISB6
ANSB6
ADIE
PCIE
Bit 6
PEIE
ADIF
CKE
—
—
—
—
(1)
(1)
(2)
(1)
SDO2SEL
INLVLA5
TRISA5
SSSEL
INLVLB5
INLVLC5
TMR0IE
TRISB5
TRISC5
SSPEN
ANSB5
RCIE
RCIF
SCIE
Bit 5
D/A
—
—
(2)
(1)
(1)
(1)
INLVLA4
SS2SEL
TRISA4
INLVLB4
INLVLC4
TRISB4
TRISC4
ANSA4
ANSB4
BOEN
Preliminary
INTE
TXIE
Bit 4
TXIF
CKP
—
—
P
(1)
(1)
(1)
INLVLA3
INLVLC3
T1GSEL
P1DSEL
TRISC3
SSP1IE
SSP1IF
SDAHT
TRISA3
ANSC3
IOCIE
In SPI Master mode, when the Sleep mode is selected,
all module clocks are halted and the transmis-
sion/reception will remain in that state until the device
wakes. After the device returns to Run mode, the mod-
ule will resume transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in Sleep mode and data
to be shifted into the SPI Transmit/Receive Shift
register. When all 8 bits have been received, the
MSSPx interrupt flag bit will be set and if enabled, will
wake the device.
Bit 3
—
—
—
—
PIC16F/LF1825/1829
S
TXCKSEL
INLVLA2
INLVLC2
P1CSEL
TMR0IF
CCP1IE
CCP1IF
TRISC2
SBCDE
TRISA2
ANSA2
ANSC2
Bit 2
R/W
—
—
—
SSPM<3:0>
INLVLC1
TRISC1
INLVLA1
P2BSEL
TMR2IE
TMR2IF
TRISA1
ANSA1
ANSC1
AHEN
Bit 1
INTF
UA
—
—
—
—
(1)
(1)
INLVLC0
CCP2SEL
TRISC0
INLVLA0
TMR1IE
TMR1IF
TRISA0
ANSA0
ANSC0
DHEN
IOCIF
Bit 0
DS41440A-page 255
BF
—
—
—
—
(1)
(1)
Register on
Page
249*
129
136
141
125
126
131
136
142
294
296
293
129
135
140
93
94
98