PIC16F1938-I/MV Microchip Technology, PIC16F1938-I/MV Datasheet - Page 183
![28KB Flash, 1KB RAM, 256B EEPROM, LCD, 1.8-5.5V 28 UQFN 4x4x0.5mm TUBE](/photos/12/13/121305/c04-152_mv_sml.jpg)
PIC16F1938-I/MV
Manufacturer Part Number
PIC16F1938-I/MV
Description
28KB Flash, 1KB RAM, 256B EEPROM, LCD, 1.8-5.5V 28 UQFN 4x4x0.5mm TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheets
1.PIC16F722-ISS.pdf
(8 pages)
2.PIC16LF1933-ISS.pdf
(508 pages)
3.PIC16LF1933-ISS.pdf
(46 pages)
4.PIC16F1938-ISS.pdf
(10 pages)
Specifications of PIC16F1938-I/MV
Core Processor
PIC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
28KB (16K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-UFQFN Exposed Pad
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
MI2C, SPI, EUSART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
25
Number Of Timers
5
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
DV164035, DV244005
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 11 Channel
On-chip Dac
5 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F722-ISS PDF datasheet
- PIC16LF1933-ISS PDF datasheet #2
- PIC16LF1933-ISS PDF datasheet #3
- PIC16F1938-ISS PDF datasheet #4
- Current page: 183 of 508
- Download datasheet (5Mb)
18.0
The module consists of a single SR Latch with multiple
Set and Reset inputs as well as separate latch outputs.
The SR Latch module includes the following features:
• Programmable input selection
• SR Latch output is available externally
• Separate Q and Q outputs
• Firmware Set and Reset
The SR Latch can be used in a variety of analog appli-
cations, including oscillator circuits, one-shot circuit,
hysteretic controllers, and analog timing applications.
18.1
The latch is a Set-Reset Latch that does not depend on
a clock source. Each of the Set and Reset inputs are
active-high. The latch can be Set or Reset by:
• Software control (SRPS and SRPR bits)
• Comparator C1 output (SYNCC1OUT)
• Comparator C2 output (SYNCC2OUT)
• SRI pin
• Programmable clock (SRCLK)
The SRPS and the SRPR bits of the SRCON0 register
may be used to set or reset the SR Latch, respectively.
The latch is Reset-dominant. Therefore, if both Set and
Reset inputs are high, the latch will go to the Reset
state. Both the SRPS and SRPR bits are self resetting
which means that a single write to either of the bits is all
that is necessary to complete a latch Set or Reset oper-
ation.
The output from Comparator C1 or C2 can be used as
the Set or Reset inputs of the SR Latch. The output of
either Comparator can be synchronized to the Timer1
clock source. See Section 17.0 “Comparator Mod-
ule” and Section 20.0 “Timer1 Module with Gate
Control” for more information.
An external source on the SRI pin can be used as the
Set or Reset inputs of the SR Latch.
An internal clock source is available that can periodically
set or reset the SR Latch. The SRCLK<2:0> bits in the
SRCON0 register are used to select the clock source
period. The SRSCKE and SRRCKE bits of the SRCON1
register enable the clock source to set or reset the SR
Latch, respectively.
2009 Microchip Technology Inc.
Note:
SR LATCH
Latch Operation
Enabling both the Set and Reset inputs
from any one source at the same time may
result in indeterminate operation, as the
Reset dominance cannot be assured.
Preliminary
18.2
The SRQEN and SRNQEN bits of the SRCON0 regis-
ter control the Q and Q latch outputs. Both of the SR
Latch outputs may be directly output to an I/O pin at the
same time. The Q latch output pin function can be
moved to an alternate pin using the SRNQSEL bit of
the APFCON register.
The applicable TRIS bit of the corresponding port must
be cleared to enable the port pin output driver.
18.3
Upon any device Reset, the SR Latch output is not ini-
tialized to a known state. The user’s firmware is
responsible for initializing the latch output before
enabling the output pins.
PIC16F193X/LF193X
Latch Output
Effects of a Reset
DS41364D-page 183
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