PIC16F1947-E/MR Microchip Technology, PIC16F1947-E/MR Datasheet - Page 112
![28KB Flash, 1KB RAM, 256B EEPROM, LCD, 1.8-5.5V 64 QFN 9x9x0.9mm TUBE](/photos/16/3/160368/qfn64_sml.jpg)
PIC16F1947-E/MR
Manufacturer Part Number
PIC16F1947-E/MR
Description
28KB Flash, 1KB RAM, 256B EEPROM, LCD, 1.8-5.5V 64 QFN 9x9x0.9mm TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheets
1.PIC16F722-ISS.pdf
(8 pages)
2.PIC16LF1933-ISS.pdf
(46 pages)
3.PIC16LF1946-IPT.pdf
(448 pages)
4.PIC16LF1946-IPT.pdf
(6 pages)
5.PIC16F1946-IPT.pdf
(8 pages)
Specifications of PIC16F1947-E/MR
Core Processor
PIC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
28KB (16K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 17x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
MI2C, SPI, EUSART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
54
Number Of Timers
5
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 17 Channel
On-chip Dac
5 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F722-ISS PDF datasheet
- PIC16LF1933-ISS PDF datasheet #2
- PIC16LF1946-IPT PDF datasheet #3
- PIC16LF1946-IPT PDF datasheet #4
- PIC16F1946-IPT PDF datasheet #5
- Current page: 112 of 448
- Download datasheet (4Mb)
PIC16F/LF1946/47
11.2
The data EEPROM is a high-endurance, byte address-
able array that has been optimized for the storage of
frequently changing information (e.g., program vari-
ables or other data that are updated often). When vari-
ables in one section change frequently, while variables
in another section do not change, it is possible to
exceed the total number of write cycles to the
EEPROM without exceeding the total number of write
cycles to a single byte. Refer to
cal
of the array must be performed. For this reason, vari-
ables that change infrequently (such as constants, IDs,
calibration, etc.) should be stored in Flash program
memory.
11.2.1
To read a data memory location, the user must write the
address to the EEADRL register, clear the EEPGD and
CFGS control bits of the EECON1 register, and then
set control bit RD. The data is available at the very next
cycle, in the EEDATL register; therefore, it can be read
in the next instruction. EEDATL will hold this value until
another read or until it is written to by the user (during
a write operation).
EXAMPLE 11-1:
DS41414B-page 112
BANKSEL EEADRL
MOVLW
MOVWF
BCF
BCF
BSF
MOVF
Note:
Specifications”. If this is the case, then a refresh
Using the Data EEPROM
DATA_EE_ADDR ;
EEADRL
EECON1, CFGS ;Deselect Config space
EECON1, EEPGD;Point to DATA memory
EECON1, RD
EEDATL, W
READING THE DATA EEPROM
MEMORY
Data EEPROM can be read regardless of
the setting of the CPD bit.
DATA EEPROM READ
;
;Data Memory
;Address to read
;EE Read
;W = EEDATL
Section 30.0 “Electri-
Preliminary
11.2.2
To write an EEPROM data location, the user must first
write the address to the EEADRL register and the data
to the EEDATL register. Then the user must follow a
specific sequence to initiate the write for each byte.
The write will not initiate if the above sequence is not
followed exactly (write 55h to EECON2, write AAh to
EECON2, then set the WR bit) for each byte. Interrupts
should be disabled during this code segment.
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times, except when
updating EEPROM. The WREN bit is not cleared
by hardware.
After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle. The WR bit will
be inhibited from being set unless the WREN bit is set.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. EEIF must be
cleared by software.
11.2.3
There are conditions when the user may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built-in. On power-up, WREN is cleared. Also, the
Power-up Timer (64 ms duration) prevents EEPROM
write.
The write initiate sequence and the WREN bit together
help prevent an accidental write during:
• Brown-out
• Power Glitch
• Software Malfunction
11.2.4
Data memory can be code-protected by programming
the CPD bit in the Configuration Word 1
to ‘0’.
When the data memory is code-protected, only the
CPU is able to read and write data to the data
EEPROM. It is recommended to code-protect the pro-
gram memory when code-protecting data memory.
This prevents anyone from replacing your program with
a program that will access the contents of the data
EEPROM.
WRITING TO THE DATA EEPROM
MEMORY
PROTECTION AGAINST SPURIOUS
WRITE
DATA EEPROM OPERATION
DURING CODE-PROTECT
2010 Microchip Technology Inc.
(Register
4-1)
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