PIC16F726-E/ML Microchip Technology, PIC16F726-E/ML Datasheet - Page 12

• Manufacturer Part Number: PIC16F726-E/ML
• Description: 14KB Flash Program, 1.8V-5.5V, 16MHz Internal Oscillator, 8b ADC, CCP, I2C/SPI,
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F726-E/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 11x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 368 B
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 3
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 11 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC16F72X/PIC16LF72X
4.0
In Program/Verify mode, the program memory and the
configuration memory can be accessed and pro-
grammed in serial fashion. ICSPDAT and ICSPCLK
are used for the data and the clock, respectively. All
commands and data words are transmitted LSb first.
Data changes on the rising edge of the ICSPCLK and
latched on the falling edge. In Program/Verify mode
both the ISCPDAT and ICSPCLK are Schmitt Trigger
inputs. The sequence that enters the device into
Program/Verify mode places all other logic into the
Reset state. Upon entering Program/Verify mode, all
I/O’s are automatically configured as high-impedance
inputs and the Program Counter (PC) is cleared.
4.1
There are 2 different methods of entering Program/
Verify mode:
• V
• V
4.1.1
To enter Program/Verify mode via the V
the following sequence must be followed:
1.
2.
3.
TABLE 4-1:
DS41332C-page 12
Load Configuration
Load Data For Program Memory
Read Data From Program Memory
Increment Address
Reset Address
Begin Internally Timed Programming
Begin Externally Timed Programming
End Externally Timed Programming
Bulk Erase Program Memory
Row Erase Program Memory
PP
DD
Hold ICSPCLK and ICSPDAT low. All other pins
should be unpowered.
Raise the voltage on MCLR from 0V to V
Raise the voltage on V
operating voltage.
– First entry mode
– First entry mode
PROGRAM/VERIFY MODE
Program/Verify Mode Entry and
Exit
V
PP
Command
– FIRST ENTRY MODE
COMMAND MAPPING FOR PIC16F72X
DD
from 0V to the desired
PP
x
x
x
x
x
x
x
x
x
x
-first method
Advance Information
IHH
Binary (MSb … LSb)
0
0
0
0
1
0
1
0
0
1
.
0
0
0
0
0
1
1
1
1
0
Mapping
0
0
1
1
1
0
0
0
0
0
The V
code prior to entering Program/Verify mode (e.g., When
the Configuration Word has MCLR disabled (MCLRE = 0),
the power-up time disabled (PWRTE = 0), and the internal
oscillator is selected (F
strongly recommended for this reason. ICSPCLK or
ICSPDAT is driven high by the user code. See the timing
diagram in Figure 8-4.
4.1.2
To enter Program/Verify mode via the V
the following sequence must be followed:
1.
2.
3.
The V
device when V
necessary to disconnect V
mode. See the timing diagram in Figure 8-5.
4.1.3
To exit Program/Verify mode take MCLR to V
lower.
4.2
The PIC16F72X and PIC16LF72X implement 10
programming commands, each six bits in length. The
commands are summarized in Table 4-1.
Commands that have data associated with them are
specified to have a minimum delay of T
command and the data. After this delay 16 clocks are
required to either clock in or clock out the 14-bit data
word. The first clock is for the Start bit and the last clock
is for the Stop bit.
0
1
0
1
1
0
0
1
0
0
Hold ICSPCLK and ICSPDAT low.
Raise the voltage on V
operating voltage.
Raise the voltage on MCLR from below V
V
PP
PP
DD
.
-first entry prevents the device from executing
-first method is useful when programming the
Program/Verify Commands
0
0
0
0
0
0
0
0
1
1
V
PROGRAM/VERIFY MODE EXIT
DD
DD
–FIRST ENTRY MODE
Hex
00h
02h
04h
06h
16h
08h
18h
0Ah
09h
11h
is already applied, for it is not
OSC
 2010 Microchip Technology Inc.
0, data (14), 0
0, data (14), 0
0, data (14), 0
Internally Timed
Internally Timed
= 10x), V
DD
DD
from 0V to the desired
to enter Program/Verify
Data/Note
PP
-first entry mode is
DLY
DD
-first method
between the
DD
DD
to
or