PIC16LF1939-E/PT Microchip Technology, PIC16LF1939-E/PT Datasheet - Page 274

• Manufacturer Part Number: PIC16LF1939-E/PT
• Description: 28KB Flash, 1KB RAM, 256B EEPROM, LCD, NanoWatt XLP 44 TQFP 10x10x1mm TRAY
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF1939-E/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 28KB (16K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F193X/LF193X
23.6.7
Master mode reception is enabled by programming the
Receive Enable bit, RCEN bit of the SSPCON2
register.
The Baud Rate Generator begins counting and on each
rollover,
(high-to-low/low-to-high) and data is shifted into the
SSPSR. After the falling edge of the eighth clock, the
receive enable flag is automatically cleared, the con-
tents of the SSPSR are loaded into the SSPBUF, the
BF flag bit is set, the SSPIF flag bit is set and the Baud
Rate Generator is suspended from counting, holding
SCL low. The MSSP is now in Idle state awaiting the
next command. When the buffer is read by the CPU,
the BF flag bit is automatically cleared. The user can
then send an Acknowledge bit at the end of reception
by setting the Acknowledge Sequence Enable, ACKEN
bit of the SSPCON2 register.
23.6.7.1
In receive operation, the BF bit is set when an address
or data byte is loaded into SSPBUF from SSPSR. It is
cleared when the SSPBUF register is read.
23.6.7.2
In receive operation, the SSPOV bit is set when 8 bits
are received into the SSPSR and the BF flag bit is
already set from a previous reception.
23.6.7.3
If the user writes the SSPBUF when a receive is
already in progress (i.e., SSPSR is still shifting in a data
byte), the WCOL bit is set and the contents of the buffer
are unchanged (the write doesn’t occur).
DS41364D-page 274
Note:
the
I
The MSSP module must be in an Idle state
before the RCEN bit is set or the RCEN bit
will be disregarded.
2
C MASTER MODE RECEPTION
BF Status Flag
SSPOV Status Flag
WCOL Status Flag
state
of
the
SCL
pin
changes
Preliminary
23.6.7.4
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Master clears SSPIF and reads the received
11. Master sets ACK value sent to slave in ACKDT
12. Masters ACK is clocked out to the Slave and
13. User clears SSPIF.
14. Steps 8-13 are repeated for each received byte
15. Master sends a not ACK or Stop to end
The user generates a Start condition by setting
the SEN bit of the SSPCON2 register.
SSPIF is set by hardware on completion of the
Start.
SSPIF is cleared by software.
User writes SSPBUF with the slave address to
transmit and the R/W bit set.
Address is shifted out the SDA pin until all 8 bits
are transmitted. Transmission begins as soon
as SSPBUF is written to.
The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
ACKSTAT bit of the SSPCON2 register.
The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
User sets the RCEN bit of the SSPCON2 register
and the Master clocks in a byte from the slave.
After the 8th falling edge of SCL, SSPIF and BF
are set.
byte from SSPUF, clears BF.
bit of the SSPCON2 register and initiates the
ACK by setting the ACKEN bit.
SSPIF is set.
from the slave.
communication.
Typical Receive Sequence:
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