PIC18F13K50T-I/SO Microchip Technology, PIC18F13K50T-I/SO Datasheet - Page 261

• Manufacturer Part Number: PIC18F13K50T-I/SO
• Description: 8 KB Flash, 512 RAM, 15 I/O, 10-bit ADC, USB 2.0 20 SOIC .300in T/R
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F13K50T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: EUSART, I2C, MSSP, SPI, USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM164127, DV164126
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164126 - KIT DEVELOPMENT USB W/PICKIT 2DM164127 - KIT DEVELOPMENT USB 18F14/13K50AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPXLT20SO1-1 - SOCKET TRANS ICE 20DIP TO 20SOIC
• Lead Free Status / Rohs Status: Details

REGISTER 22-5:
 2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5-4
bit 3
bit 2
bit 1-0
Note 1:
UOWN
R/W-x
2:
3:
(1)
This bit must be initialized by the user to the desired value prior to enabling the USB module.
This bit is ignored unless DTSEN = 1.
If these bits are set, USB communication may not work. Hence, these bits should always be maintained as
‘0’.
UOWN: USB Own bit
0 = The microcontroller core owns the BD and its corresponding buffer
DTS: Data Toggle Synchronization bit
1 = Data 1 packet
0 = Data 0 packet
Unimplemented: These bits should always be programmed to ‘0’
DTSEN: Data Toggle Synchronization Enable bit
1 = Data toggle synchronization is enabled; data packets with incorrect Sync value will be ignored
0 = No data toggle synchronization is performed
BSTALL: Buffer Stall Enable bit
1 = Buffer stall enabled; STALL handshake issued if a token is received that would use the BD in the
0 = Buffer stall disabled
BC<9:8>: Byte Count 9 and 8 bits
The byte count bits represent the number of bytes that will be transmitted for an IN token or received
during an OUT token. Together with BC<7:0>, the valid byte counts are 0-1023.
DTS
R/W-x
except for a SETUP transaction, which is accepted even if the data toggle bits do not match
given location (UOWN bit remains set, BD value is unchanged)
BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER (BD0STAT THROUGH
BD31STAT), CPU MODE (DATA IS WRITTEN TO THE SIDE)
(2)
W = Writable bit
‘1’ = Bit is set
—
U-0
(3)
(1)
—
U-0
Preliminary
(3)
(2)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
DTSEN
R/W-x
PIC18F/LF1XK50
BSTALL
R/W-x
(3)
.
x = Bit is unknown
R/W-x
BC9
DS41350E-page 261
R/W-x
BC8
bit 0