PIC18F13K50T-I/SO Microchip Technology, PIC18F13K50T-I/SO Datasheet - Page 91

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PIC18F13K50T-I/SO

Manufacturer Part Number
PIC18F13K50T-I/SO
Description
8 KB Flash, 512 RAM, 15 I/O, 10-bit ADC, USB 2.0 20 SOIC .300in T/R
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr

Specifications of PIC18F13K50T-I/SO

Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
14
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
EUSART, I2C, MSSP, SPI, USB
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
15
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM164127, DV164126
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 11 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164126 - KIT DEVELOPMENT USB W/PICKIT 2DM164127 - KIT DEVELOPMENT USB 18F14/13K50AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPXLT20SO1-1 - SOCKET TRANS ICE 20DIP TO 20SOIC
Lead Free Status / Rohs Status
 Details
REGISTER 9-8:
REGISTER 9-9:
REGISTER 9-10:
 2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-4
bit 3-0
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-4
bit 3-0
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-4
bit 3-0
WPUB7
IOCB7
LATB7
R/W-1
R/W-0
R/W-x
WPUB<7:4>: Weak Pull-up Enable bit
1 = Pull-up enabled
0 = Pull-up disabled
Unimplemented: Read as ‘0’
IOCB<7:4>: Interrupt-on-change bits
1 = Interrupt-on-change enabled
0 = Interrupt-on-change disabled
Unimplemented: Read as ‘0’
LATB<7:4>: RB<7:4> Port I/O Output Latch Register bits
Unimplemented: Read as ‘0’
WPUB6
IOCB6
LATB6
R/W-1
R/W-0
R/W-x
WPUB: WEAK PULL-UP PORTB REGISTER
IOCB: INTERRUPT-ON-CHANGE PORTB REGISTER
LATB: PORTB DATA LATCH REGISTER
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
WPUB5
IOCB5
LATB5
R/W-1
R/W-0
R/W-x
WPUB4
IOCB4
LATB4
R/W-1
R/W-0
R/W-x
Preliminary
U = Unimplemented bit, read as ‘0’
U = Unimplemented bit, read as ‘0’
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
‘0’ = Bit is cleared
‘0’ = Bit is cleared
U-0
U-0
U-0
PIC18F/LF1XK50
U-0
U-0
U-0
x = Bit is unknown
x = Bit is unknown
x = Bit is unknown
U-0
U-0
U-0
DS41350E-page 91
U-0
U-0
U-0
bit 0
bit 0
bit 0

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