PIC18F2221-E/ML Microchip Technology, PIC18F2221-E/ML Datasheet
PIC18F2221-E/ML
Specifications of PIC18F2221-E/ML
Related parts for PIC18F2221-E/ML
PIC18F2221-E/ML Summary of contents
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... PIC18F2221/2321/4221/4321 Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology © 2009 Microchip Technology Inc. Family Data Sheet DS39689F ...
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... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... PIC18F2221/2321/4221/4321 FAMILY 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology Power-Managed Modes: • Run: CPU On, Peripherals On • Idle: CPU Off, Peripherals On • Sleep: CPU Off, Peripherals Off • Idle mode Currents Down to 2.5 μA Typical • Sleep mode Currents Down to 500 nA Typical • ...
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... PIC18F2221/2321/4221/4321 FAMILY Pin Diagrams 28-Pin SPDIP, SOIC, SSOP MCLR/V RA0/AN0 RA1/AN1 RA2/AN2/V -/CV REF RA3/AN3/V RA4/T0CKI/C1OUT RA5/AN4/SS/HLVDIN/C2OUT OSC1/CLKI/RA7 OSC2/CLKO/RA6 RC0/T1OSO/T13CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL 28-Pin QFN RA2/AN2/V REF- RA3/AN3/V RA4/T0CKI/C1OUT RA5/AN4/SS/HLVDIN/C2OUT OSC1/CLKI/RA7 OSC2/CLKO/RA6 Note 1: RB3 is the alternate pin for CCP2 multiplexing. DS39689F-page 4 28 ...
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... PIC18F2221/2321/4221/4321 FAMILY Pin Diagrams (Continued) 40-Pin PDIP MCLR/V PP RA0/AN0 RA1/AN1 RA2/AN2/V -/CV REF RA3/AN3/V RA4/T0CKI/C1OUT RA5/AN4/SS/HLVDIN/C2OUT RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 OSC1/CLKI/RA7 OSC2/CLKO/RA6 RC0/T1OSO/T13CKI RC1/T1OSI/CCP2 RC2/CCP1/P1A RC3/SCK/SCL RD0/PSP0 RD1/PSP1 (2) 44-Pin QFN RC7/RX/DT RD4/PSP4 RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D RB0/INT0/FLT0/AN12 RB1/INT1/AN10 RB2/INT2/AN8 Note 1: RB3 is the alternate pin for CCP2 multiplexing. ...
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... PIC18F2221/2321/4221/4321 FAMILY Pin Diagrams (Continued) 44-Pin TQFP RC7/RX/DT RD4/PSP4 RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D RB0/INT0/FLT0/AN12 RB1/INT1/AN10 RB2/INT2/AN8 (1) RB3/AN9/CCP2 Note 1: RB3 is the alternate pin for CCP2 multiplexing. DS39689F-page RC0/T1OSO/T13CKI 2 31 OSC2/CLKO/RA6 3 30 OSC1/CLKI/RA7 4 PIC18F4221 PIC18F4321 RE2/CS/AN7 27 7 RE1/WR/AN6 8 26 RE0/RD/AN5 9 25 RA5/AN4/SS/HLVDIN/C2OUT RA4/T0CKI/C1OUT 11 © 2009 Microchip Technology Inc. ...
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... Appendix E: Migration From Mid-Range to Enhanced Devices ......................................................................................................... 388 Appendix F: Migration From High-End to Enhanced Devices............................................................................................................ 388 Index ................................................................................................................................................................................................. 389 The Microchip Web Site ..................................................................................................................................................................... 399 Customer Change Notification Service .............................................................................................................................................. 399 Customer Support .............................................................................................................................................................................. 399 Reader Response .............................................................................................................................................................................. 400 PIC18F2221/2321/4221/4321 Product Identification System ............................................................................................................ 401 © 2009 Microchip Technology Inc. DS39689F-page 7 ...
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... PIC18F2221/2321/4221/4321 FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. ...
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... Microchip Technology Inc. 1.1.2 MULTIPLE OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC18F2221/2321/4221/4321 family offer ten different oscillator options, allowing users a wide range of choices in developing application hardware. These include: • Four Crystal modes, using crystals or ceramic resonators. ...
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... Boot Block at the top of program memory, it becomes possible to create an application that can update itself in the field. • Extended Instruction Set: The PIC18F2221/ 2321/4221/4321 family introduces an optional extension to the PIC18 instruction set, which adds 8 new instructions and an Indexed Addressing mode ...
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... PIC18F2221/2321/4221/4321 FAMILY TABLE 1-1: DEVICE FEATURES Features Operating Frequency Program Memory (Bytes) Program Memory (Instructions) Data Memory (Bytes) Data EEPROM Memory (Bytes) Interrupt Sources I/O Ports Ports (E) Timers Capture/Compare/PWM Modules Enhanced Capture/Compare/ PWM Modules Serial Communications Enhanced USART Parallel Communications (PSP) ...
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... PIC18F2221/2321/4221/4321 FAMILY FIGURE 1-1: PIC18F2221/2321 (28-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> 8 inc/dec logic PCLATU PCLATH 21 20 PCU PCH PCL Program Counter 31 Level Stack Address Latch Program Memory STKPTR (4 Kbytes) Data Latch 8 Table Latch ROM Latch Instruction Bus <16> IR State Machine ...
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... PIC18F2221/2321/4221/4321 FAMILY FIGURE 1-2: PIC18F4221/4321 (40/44-PIN) BLOCK DIAGRAM Table Pointer<21> 8 inc/dec logic PCLATU PCLATH 21 20 PCU PCH PCL Program Counter 31 Level Stack Address Latch Program Memory STKPTR (8 Kbytes) Data Latch 8 Table Latch ROM Latch Instruction Bus <16> IR State Machine Instruction Control Signals Decode & ...
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... PIC18F2221/2321/4221/4321 FAMILY TABLE 1-2: PIC18F2221/2321 PINOUT I/O DESCRIPTIONS Pin Number SPDIP, Pin Name SOIC, QFN SSOP MCLR/V /RE3 MCLR V PP RE3 OSC1/CLKI/RA7 9 6 OSC1 CLKI RA7 OSC2/CLKO/RA6 10 7 OSC2 CLKO RA6 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels ...
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... PIC18F2221/2321/4221/4321 FAMILY TABLE 1-2: PIC18F2221/2321 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number SPDIP, Pin Name SOIC, QFN SSOP RA0/AN0 2 27 RA0 AN0 RA1/AN1 3 28 RA1 AN1 RA2/AN2/V -/ REF REF RA2 AN2 V - REF CV REF RA3/AN3 REF RA3 AN3 V + REF RA4/T0CKI/C1OUT 6 3 RA4 T0CKI ...
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... PIC18F2221/2321/4221/4321 FAMILY TABLE 1-2: PIC18F2221/2321 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number SPDIP, Pin Name SOIC, QFN SSOP RB0/INT0/FLT0/AN12 21 18 RB0 INT0 FLT0 AN12 RB1/INT1/AN10 22 19 RB1 INT1 AN10 RB2/INT2/AN8 23 20 RB2 INT2 AN8 RB3/AN9/CCP2 24 21 RB3 AN9 (2) CCP2 RB4/KBI0/AN11 25 22 RB4 ...
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... PIC18F2221/2321/4221/4321 FAMILY TABLE 1-2: PIC18F2221/2321 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number SPDIP, Pin Name SOIC, QFN SSOP RC0/T1OSO/T13CKI 11 8 RC0 T1OSO T13CKI RC1/T1OSI/CCP2 12 9 RC1 T1OSI (1) CCP2 RC2/CCP1 13 10 RC2 CCP1 RC3/SCK/SCL 14 11 RC3 SCK SCL RC4/SDI/SDA 15 12 RC4 SDI SDA ...
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... PIC18F2221/2321/4221/4321 FAMILY TABLE 1-3: PIC18F4221/4321 PINOUT I/O DESCRIPTIONS Pin Number Pin Name PDIP QFN TQFP MCLR/V /RE3 MCLR V PP RE3 OSC1/CLKI/RA7 13 32 OSC1 CLKI RA7 OSC2/CLKO/RA6 14 33 OSC2 CLKO RA6 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels ...
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... PIC18F2221/2321/4221/4321 FAMILY TABLE 1-3: PIC18F4221/4321 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP QFN TQFP RA0/AN0 2 19 RA0 AN0 RA1/AN1 3 20 RA1 AN1 RA2/AN2/V -/ REF REF RA2 AN2 V - REF CV REF RA3/AN3 REF RA3 AN3 V + REF RA4/T0CKI/C1OUT 6 23 RA4 T0CKI C1OUT ...
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... PIC18F2221/2321/4221/4321 FAMILY TABLE 1-3: PIC18F4221/4321 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP QFN TQFP RB0/INT0/FLT0/AN12 33 9 RB0 INT0 FLT0 AN12 RB1/INT1/AN10 34 10 RB1 INT1 AN10 RB2/INT2/AN8 35 11 RB2 INT2 AN8 RB3/AN9/CCP2 36 12 RB3 AN9 (2) CCP2 RB4/KBI0/AN11 37 14 RB4 KBI0 ...
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... PIC18F2221/2321/4221/4321 FAMILY TABLE 1-3: PIC18F4221/4321 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP QFN TQFP RC0/T1OSO/T13CKI 15 34 RC0 T1OSO T13CKI RC1/T1OSI/CCP2 16 35 RC1 T1OSI (1) CCP2 RC2/CCP1/P1A 17 36 RC2 CCP1 P1A RC3/SCK/SCL 18 37 RC3 SCK SCL RC4/SDI/SDA 23 42 RC4 SDI SDA ...
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... PIC18F2221/2321/4221/4321 FAMILY TABLE 1-3: PIC18F4221/4321 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP QFN TQFP RD0/PSP0 19 38 RD0 PSP0 RD1/PSP1 20 39 RD1 PSP1 RD2/PSP2 21 40 RD2 PSP2 RD3/PSP3 22 41 RD3 PSP3 RD4/PSP4 27 2 RD4 PSP4 RD5/PSP5/P1B 28 3 RD5 PSP5 P1B ...
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... PIC18F2221/2321/4221/4321 FAMILY TABLE 1-3: PIC18F4221/4321 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP QFN TQFP RE0/RD/AN5 8 25 RE0 RD AN5 RE1/WR/AN6 9 26 RE1 WR AN6 RE2/CS/AN7 10 27 RE2 CS AN7 RE3 — — — 13 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels ...
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... PIC18F2221/2321/4221/4321 FAMILY NOTES: DS39689F-page 24 © 2009 Microchip Technology Inc. ...
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... GUIDELINES FOR GETTING STARTED WITH PIC18F MICROCONTROLLERS 2.1 Basic Connection Requirements Getting started with the PIC18F2221/2321/4221/4321 family family of 8-bit microcontrollers requires attention to a minimal set of device pin connections before proceeding with development. The following pins must always be connected: • All V ...
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... PIC18F2221/2321/4221/4321 FAMILY 2.2 Power Supply Pins 2.2.1 DECOUPLING CAPACITORS The use of decoupling capacitors on every pair of power supply pins, such required. SS Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: A 0.1 μF (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device with a resonance frequency in the range of 200 MHz and higher ...
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... PIC18F2221/2321/4221/4321 FAMILY 2.4 ICSP Pins The PGC and PGD pins are used for In-Circuit Serial Programming (ICSP) and debugging purposes recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to ...
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... PIC18F2221/2321/4221/4321 FAMILY NOTES: DS39689F-page 28 © 2009 Microchip Technology Inc. ...
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... PIC18F2221/2321/4221/4321 FAMILY 3.0 OSCILLATOR CONFIGURATIONS 3.1 Oscillator Types The PIC18F2221/2321/4221/4321 family of devices can be operated in ten different oscillator modes. The user can program the Configuration bits, FOSC<3:0>, in Configuration Register 1H to select one of these ten modes Low-Power Crystal 2. XT Crystal/Resonator 3. HS High-Speed Crystal/Resonator 4 ...
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... PIC18F2221/2321/4221/4321 FAMILY TABLE 3-2: CAPACITOR SELECTION FOR QUARTZ CRYSTALS Typical Capacitor Values Crystal Tested: Osc Type Freq kHz MHz MHz MHz MHz MHz MHz 22 pF Capacitor values are for design guidance only. Different capacitor values may be required to produce acceptable oscillator operation. The user should test ...
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... PIC18F2221/2321/4221/4321 FAMILY 3.4 RC Oscillator For timing insensitive applications, the RC and RCIO Oscillator modes offer additional cost savings. The actual oscillator frequency is a function of several factors: • supply voltage • values of the external resistor (R EXT capacitor (C ) EXT • operating temperature Given the same device, operating voltage, temperature and component values, there will also be unit-to-unit frequency variations ...
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... PIC18F2221/2321/4221/4321 FAMILY 3.6 Internal Oscillator Block The PIC18F2221/2321/4221/4321 family of devices includes an internal oscillator block which generates two different clock signals; either can be used as the microcontroller’s clock source. This may eliminate the need for external oscillator circuits on the OSC1 and/or OSC2 pins. ...
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... PIC18F2221/2321/4221/4321 FAMILY 3.6.4 PLL IN INTOSC MODES The 4x Phase Locked Loop (PLL) can be used with the internal oscillator block to produce faster device clock speeds than are normally possible with the internal oscillator sources. When enabled, the PLL produces a clock speed of 16 MHz or 32 MHz. ...
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... PIC18F2221/2321/4221/4321 FAMILY 3.6.5.1 Compensating with the EUSART An adjustment may be required when the EUSART begins to generate framing errors or receives data with errors while in Asynchronous mode. Framing errors indicate that the device clock frequency is too high. To adjust for this, decrement the value in OSCTUNE to reduce the clock frequency ...
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... The INTRC source is also used as the clock source for several special features, such as the WDT and Fail-Safe Clock Monitor. The clock sources for the PIC18F2221/2321/4221/4321 family of devices are shown in Figure 3-11. See Section 24.0 “Special Features of the CPU” for Configuration register details ...
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... Timer1 oscillator starts. 3.7.2 OSCILLATOR TRANSITIONS The PIC18F2221/2321/4221/4321 family of devices con- tains circuitry to prevent clock “glitches” when switching between clock sources. A short pause in the device clock occurs during the clock switch. The length of this pause is the sum of two cycles of the old clock source and three to four cycles of the new clock source ...
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... PIC18F2221/2321/4221/4321 FAMILY REGISTER 3-2: OSCCON: OSCILLATOR CONTROL REGISTER R/W-0 R/W-1 IDLEN IRCF2 bit 7 bit 7 IDLEN: Idle Enable bit 1 = Device enters an Idle mode when a SLEEP instruction is executed 0 = Device enters Sleep mode when a SLEEP instruction is executed bit 6-4 IRCF<2:0>: Internal Oscillator Frequency Select bits ...
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... PIC18F2221/2321/4221/4321 FAMILY 3.8 Effects of Power-Managed Modes on the Various Clock Sources When PRI_IDLE mode is selected, the designated pri- mary oscillator continues to run without interruption. For all other power-managed modes, the oscillator using the OSC1 pin is disabled. The OSC1 pin (and OSC2 pin in Crystal Oscillator modes) will stop oscillating ...
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... PIC18F2221/2321/4221/4321 FAMILY 4.0 POWER-MANAGED MODES PIC18F2221/2321/4221/4321 family devices offer a total of seven operating modes for more efficient power-management. These modes provide a variety of options for selective power conservation in applications where resources may be limited (i.e., battery-powered devices). There are three categories of power-managed modes: • Run modes • ...
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... PIC18F2221/2321/4221/4321 FAMILY 4.1.3 CLOCK TRANSITIONS AND STATUS INDICATORS The length of the transition between clock sources is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Three bits indicate the current clock source and its status. They are: • ...
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... PIC18F2221/2321/4221/4321 FAMILY FIGURE 4-1: TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE T1OSI OSC1 CPU Clock Peripheral Clock Program PC Counter Note 1: Clock transition typically occurs within 2-4 T FIGURE 4-2: TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL) Q1 T1OSI OSC1 T OST PLL Clock Output ...
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... PIC18F2221/2321/4221/4321 FAMILY If the IRCF bits and the INTSRC bit are all clear, the INTOSC output is not enabled and the IOFS bit will remain clear; there will be no indication of the current clock source. The INTRC source is providing the device clocks. If the IRCF bits are changed from all clear (thus, ...
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... PIC18F2221/2321/4221/4321 FAMILY 4.3 Sleep Mode The power-managed Sleep mode in the PIC18F2221/ 2321/4221/4321 family devices is identical to the leg- acy Sleep mode offered in all other PIC devices entered by clearing the IDLEN bit (the default state on device Reset) and executing the SLEEP instruction. This shuts down the selected oscillator (Figure 4-5). All clock source status bits are cleared ...
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... PIC18F2221/2321/4221/4321 FAMILY 4.4.1 PRI_IDLE MODE This mode is unique among the three low-power Idle modes, in that it does not disable the primary device clock. For timing sensitive applications, this allows for the fastest resumption of device operation with its more accurate primary clock source, since the clock source does not have to “ ...
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... PIC18F2221/2321/4221/4321 FAMILY 4.4.3 RC_IDLE MODE In RC_IDLE mode, the CPU is disabled but the periph- erals continue to be clocked from the internal oscillator block using the INTOSC multiplexer. This mode allows for controllable power conservation during Idle periods. From RC_RUN, this mode is entered by setting the IDLEN bit and executing a SLEEP instruction ...
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... PIC18F2221/2321/4221/4321 FAMILY 4.5.4 EXIT WITHOUT AN OSCILLATOR START-UP DELAY Certain exits from power-managed modes do not invoke the OST at all. There are two cases: • PRI_IDLE mode, where the primary clock source is not stopped; and • the primary clock source is not any of the LP, XT HSPLL modes ...
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... PIC18F2221/2321/4221/4321 FAMILY 5.0 RESET The PIC18F2221/2321/4221/4321 differentiate between various kinds of Reset: a) Power-on Reset (POR) b) MCLR Reset during normal operation c) MCLR Reset during power-managed modes d) Watchdog Timer (WDT) Reset (during execution) e) Programmable Brown-out Reset (BOR) f) RESET Instruction g) Stack Full Reset h) Stack Underflow Reset ...
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... PIC18F2221/2321/4221/4321 FAMILY REGISTER 5-1: RCON: RESET CONTROL REGISTER R/W-0 R/W-1 IPEN SBOREN bit 7 bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 SBOREN: BOR Software Enable bit If BOREN<1:0> BOR is enabled 0 = BOR is disabled If BOREN< ...
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... The MCLR pin is not driven low by any internal Resets, including the WDT. In PIC18F2221/2321/4221/4321 family devices, the MCLR input can be disabled with the MCLRE Configu- ration bit. When MCLR is disabled, the pin becomes a digital input. See Section 11.5 “PORTE, TRISE and LATE Registers” ...
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... PIC18F2221/2321/4221/4321 FAMILY 5.4 Brown-out Reset (BOR) PIC18F2221/2321/4221/4321 family devices implement a BOR circuit that provides the user with a number of configuration and power-saving options. The BOR is controlled by the BORV<1:0> and BOREN<1:0> Configuration bits. There are a total of four BOR configurations which are summarized in Table 5-1. ...
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... These timers are: • Power-up Timer (PWRT) • Oscillator Start-up Timer (OST) • PLL Lock Time-out 5.5.1 POWER-UP TIMER (PWRT) The Power-up Timer (PWRT) of the PIC18F2221/ 2321/4221/4321 family devices is an 11-bit counter which uses the INTRC source as the clock input. This yields an ...
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... PIC18F2221/2321/4221/4321 FAMILY FIGURE 5-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 5-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 5-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO V ...
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... PIC18F2221/2321/4221/4321 FAMILY FIGURE 5-6: SLOW RISE TIME (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 5-7: TIME-OUT SEQUENCE ON POR w/PLL ENABLED (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT PLL TIME-OUT INTERNAL RESET Note 1024 clock cycles. ...
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... PIC18F2221/2321/4221/4321 FAMILY 5.6 Reset State of Registers Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. The other registers are forced to a “Reset state” depending on the type of Reset that occurred. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal oper- ation ...
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... PIC18F2221/2321/4221/4321 FAMILY TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS Register Applicable Devices TOSU 2221 2321 4221 4321 TOSH 2221 2321 4221 4321 TOSL 2221 2321 4221 4321 STKPTR 2221 2321 4221 4321 PCLATU 2221 2321 4221 4321 PCLATH 2221 2321 4221 4321 ...
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... PIC18F2221/2321/4221/4321 FAMILY TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices FSR1H 2221 2321 4221 4321 FSR1L 2221 2321 4221 4321 BSR 2221 2321 4221 4321 INDF2 2221 2321 4221 4321 POSTINC2 2221 2321 4221 4321 POSTDEC2 2221 2321 4221 4321 ...
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... PIC18F2221/2321/4221/4321 FAMILY TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices ADRESH 2221 2321 4221 4321 ADRESL 2221 2321 4221 4321 ADCON0 2221 2321 4221 4321 ADCON1 2221 2321 4221 4321 ADCON2 2221 2321 4221 4321 CCPR1H 2221 2321 4221 4321 ...
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... PIC18F2221/2321/4221/4321 FAMILY TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices IPR2 2221 2321 4221 4321 PIR2 2221 2321 4221 4321 PIE2 2221 2321 4221 4321 IPR1 2221 2321 4221 4321 2221 2321 4221 4321 PIR1 2221 2321 4221 4321 ...
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... NOP instruction). The PIC18F2221 and PIC18F4221 each have 4 Kbytes of Flash memory and can store up to 2048 single-word instructions. The PIC18F2321 and PIC18F4321 each have 8 Kbytes of Flash memory and can store up to 4096 single-word instructions ...
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... PIC18F2221/2321/4221/4321 FAMILY 6.1.1 PROGRAM COUNTER The Program Counter (PC) specifies the address of the instruction to fetch for execution. The bits wide and is contained in three separate 8-bit registers. The low byte, known as the PCL register, is both readable and writable. The high byte, or PCH register, contains the PC< ...
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... PIC18F2221/2321/4221/4321 FAMILY 6.1.2.2 Return Stack Pointer (STKPTR) The STKPTR register (Register 6-1) contains the Stack Pointer value, the STKFUL (Stack Full) status bit and the STKUNF (Stack Underflow) status bits. The value of the Stack Pointer can be 0 through 31. The Stack Pointer increments before values are pushed onto the stack and decrements after values are popped off the stack ...
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... PIC18F2221/2321/4221/4321 FAMILY 6.1.2.4 Stack Full and Underflow Resets Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit in Configuration Register 4L. When STVREN is set, a full or underflow will set the appropriate STKFUL or STKUNF bit and then cause a device Reset. When ...
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... PIC18F2221/2321/4221/4321 FAMILY 6.2 PIC18 Instruction Cycle 6.2.1 CLOCKING SCHEME The microcontroller clock input, whether from an internal or external source, is internally divided by four to generate four non-overlapping quadrature clocks (Q1, Q2, Q3 and Q4). Internally, the program counter is incremented on every Q1; the instruction is fetched from the program memory and latched into the Instruction Register (IR) during Q4 ...
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... PIC18F2221/2321/4221/4321 FAMILY 6.2.3 INSTRUCTIONS IN PROGRAM MEMORY The program memory is addressed in bytes. Instruc- tions are stored as two bytes or four bytes in program memory. The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSb = 0). To maintain alignment with instruction boundaries, the PC increments in steps of 2 and the LSb will always read ‘ ...
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... RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. The memory space is divided into as many as 16 banks that contain 256 bytes each; PIC18F2221/ 2321/4221/4321 family devices implement 2 banks. Figure 6-5 shows the data memory organization for the PIC18F2221/2321/4221/4321 family devices ...
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... PIC18F2221/2321/4221/4321 FAMILY FIGURE 6-5: DATA MEMORY MAP FOR PIC18F2221/2321/4221/4321 FAMILY DEVICES BSR<3:0> 00h = 0000 Bank 0 FFh = 0001 Bank 1 = 0010 Bank 1110 Bank 14 00h = 1111 Bank 15 FFh DS39689F-page 66 Data Memory Map 000h Access RAM 07Fh 080h GPR 0FFh 100h GPR 1FFh Unused Read ‘ ...
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... PIC18F2221/2321/4221/4321 FAMILY FIGURE 6-6: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING) (1) BSR (2) Bank Select Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank. 2: The MOVFF instruction embeds the entire 12-bit address in the instruction. ...
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... RAM. SFRs start at the top of data memory (FFFh) and extend downward to occupy the top half of Bank 15 (F80h to FFFh). A list of these registers is given in Table 6-1 and Table 6-2. TABLE 6-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F2221/2321/4221/4321 FAMILY DEVICES Address Name Address ...
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... PIC18F2221/2321/4221/4321 FAMILY TABLE 6-2: REGISTER FILE SUMMARY (PIC18F2221/2321/4221/4321) File Name Bit 7 Bit 6 Bit 5 TOSU — — — TOSH Top-of-Stack High Byte (TOS<15:8>) TOSL Top-of-Stack Low Byte (TOS<7:0>) (6) (6) STKPTR STKFUL STKUNF — PCLATU — — Holding Register for PC<21:16> PCLATH Holding Register for PC<15:8> ...
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... PIC18F2221/2321/4221/4321 FAMILY TABLE 6-2: REGISTER FILE SUMMARY (PIC18F2221/2321/4221/4321) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 TMR0H Timer0 Register High Byte TMR0L Timer0 Register Low Byte T0CON TMR0ON T08BIT T0CS OSCCON IDLEN IRCF2 IRCF1 HLVDCON VDIRMAG — IRVST WDTCON — — — (1) RCON ...
Page 71
... PIC18F2221/2321/4221/4321 FAMILY TABLE 6-2: REGISTER FILE SUMMARY (PIC18F2221/2321/4221/4321) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 SPBRGH EUSART Baud Rate Generator Register High Byte SPBRG EUSART Baud Rate Generator Register Low Byte RCREG EUSART Receive Register TXREG EUSART Transmit Register TXSTA CSRC TX9 ...
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... PIC18F2221/2321/4221/4321 FAMILY 6.3.5 STATUS REGISTER The STATUS register, shown in Register 6-2, contains the arithmetic status of the ALU. As with any other SFR, it can be the operand for any instruction. If the STATUS register is the destination for an instruc- tion that affects the Z, DC bits, the results of the instruction are not written ...
Page 73
... PIC18F2221/2321/4221/4321 FAMILY 6.4 Data Addressing Modes Note: The execution of some instructions in the core PIC18 instruction set are changed when the PIC18 extended instruction set is enabled. See Section 6.5 “Data Memory and the Extended Instruction Set” for more information. The data memory space can be addressed in several ways ...
Page 74
... PIC18F2221/2321/4221/4321 FAMILY 6.4.3.1 FSR Registers and the INDF Operand At the core of indirect addressing are three sets of registers: FSR0, FSR1 and FSR2. Each represents a pair of 8-bit registers, FSRnH and FSRnL. The four upper bits of the FSRnH register are not used so each FSR pair holds a 12-bit value. This represents a value that can address the entire range of the data memory in a linear fashion ...
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... PIC18F2221/2321/4221/4321 FAMILY The PLUSW register can be used to implement a form of indexed addressing in the data memory space. By manipulating the value in the W register, users can reach addresses that are fixed offsets from pointer addresses. In some applications, this can be used to implement some powerful program control structure, such as software stacks, inside of data memory ...
Page 76
... PIC18F2221/2321/4221/4321 FAMILY FIGURE 6-8: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) EXAMPLE INSTRUCTION: ADDWF (Opcode: 0010 01da ffff ffff) When ‘a’ and ‘f’ ≥ 60h: The instruction executes in Direct Forced mode. ‘f’ is inter- ...
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... PIC18F2221/2321/4221/4321 FAMILY 6.5.3 MAPPING THE ACCESS BANK IN INDEXED LITERAL OFFSET ADDRESSING MODE The use of Indexed Literal Offset Addressing mode effectively changes how the first 96 locations of Access RAM (00h to 5Fh) are mapped. Rather than containing just the contents of the bottom half of Bank 0, this mode maps the contents from Bank 0 and a user-defined “ ...
Page 78
... PIC18F2221/2321/4221/4321 FAMILY NOTES: DS39689F-page 78 © 2009 Microchip Technology Inc. ...
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... PIC18F2221/2321/4221/4321 FAMILY 7.0 FLASH PROGRAM MEMORY The Flash program memory is readable, writable and erasable during normal operation over the entire V range. A read from program memory is executed on one byte at a time. A write to program memory is executed on blocks of 8 bytes at a time. Program memory is erased in blocks of 64 bytes at a time ...
Page 80
... PIC18F2221/2321/4221/4321 FAMILY FIGURE 7-2: TABLE WRITE OPERATION (1) Table Pointer TBLPTRU TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer actually points to one of 64 holding registers, the address of which is determined by TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in Section 7.5 “Writing to Flash Program Memory”. ...
Page 81
... PIC18F2221/2321/4221/4321 FAMILY REGISTER 7-1: EECON1: DATA EEPROM CONTROL REGISTER 1 R/W-x R/W-x EEPGD CFGS bit 7 bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Access Configuration registers ...
Page 82
... PIC18F2221/2321/4221/4321 FAMILY 7.2.2 TABLAT – TABLE LATCH REGISTER The Table Latch (TABLAT 8-bit register mapped into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. 7.2.3 TBLPTR – TABLE POINTER ...
Page 83
... PIC18F2221/2321/4221/4321 FAMILY 7.3 Reading the Flash Program Memory The TBLRD instruction is used to retrieve data from program memory and place it into data RAM. Table reads from program memory are performed one byte at a time. FIGURE 7-4: READS FROM FLASH PROGRAM MEMORY (Even Byte Address) ...
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... PIC18F2221/2321/4221/4321 FAMILY 7.4 Erasing Flash Program Memory The minimum erase block is 32 words or 64 bytes. Only through the use of an external programmer, or through ICSP control, can larger blocks of program memory be bulk erased. Word erase in the Flash array is not supported. When initiating an erase sequence from the micro- controller itself, a block of 64 bytes of program memory is erased ...
Page 85
... PIC18F2221/2321/4221/4321 FAMILY 7.5 Writing to Flash Program Memory The minimum programming block is 4 words or 8 bytes. Word or byte programming is not supported. Table writes are used internally to load the holding registers needed to program the Flash memory. There are 8 holding registers used by the table writes for programming ...
Page 86
... PIC18F2221/2321/4221/4321 FAMILY EXAMPLE 7-3: WRITING TO FLASH PROGRAM MEMORY MOVLW D'64' MOVWF COUNTER MOVLW BUFFER_ADDR_HIGH MOVWF FSR0H MOVLW BUFFER_ADDR_LOW MOVWF FSR0L MOVLW CODE_ADDR_UPPER MOVWF TBLPTRU MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL READ_BLOCK TBLRD*+ MOVF TABLAT, W MOVWF POSTINC0 DECFSZ COUNTER BRA ...
Page 87
... PIC18F2221/2321/4221/4321 FAMILY EXAMPLE 7-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED) PROGRAM_MEMORY BCF INTCON, GIE MOVLW 55h MOVWF EECON2 MOVLW 0AAh MOVWF EECON2 BSF EECON1, WR NOP BSF INTCON, GIE DECFSZ COUNTER_HI GOTO PROGRAM_LOOP BCF EECON1, WREN 7.5.2 WRITE VERIFY Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value ...
Page 88
... PIC18F2221/2321/4221/4321 FAMILY NOTES: DS39689F-page 88 © 2009 Microchip Technology Inc. ...
Page 89
... PIC18F2221/2321/4221/4321 FAMILY 8.0 DATA EEPROM MEMORY The data EEPROM is a nonvolatile memory array, separate from the data RAM and program memory, that is used for long-term storage of program data not directly mapped in either the register file or program memory space but is indirectly addressed through the Special Function Registers (SFRs) ...
Page 90
... PIC18F2221/2321/4221/4321 FAMILY REGISTER 8-1: EECON1: DATA EEPROM CONTROL REGISTER 1 R/W-x R/W-x EEPGD CFGS bit 7 bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Access Configuration registers ...
Page 91
... PIC18F2221/2321/4221/4321 FAMILY 8.2 Reading the Data EEPROM Memory To read a data memory location, the user must write the address to the EEADR register, clear the EEPGD control bit (EECON1<7>) and then set control bit, RD (EECON1<0>). The data is available on the very next instruction cycle; therefore, the EEDATA register can be read by the next instruction ...
Page 92
... PIC18F2221/2321/4221/4321 FAMILY 8.5 Operation During Code-Protect Data EEPROM memory has its own code-protect bits in Configuration Words. External read operations are disabled if code protection is enabled. The microcontroller itself can both read and write to the internal data EEPROM, regardless of the state of the code-protect Configuration bit. Refer to Section 24.0 “ ...
Page 93
... PIC18F2221/2321/4221/4321 FAMILY TABLE 8-1: REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY Name Bit 7 Bit 6 INTCON GIE/GIEH PEIE/GIEL TMR0IE EEADR EEPROM Address Register EEDATA EEPROM Data Register EECON2 EEPROM Control Register 2 (not a physical register) EECON1 EEPGD CFGS IPR2 OSCFIP CMIP PIR2 OSCFIF CMIF ...
Page 94
... PIC18F2221/2321/4221/4321 FAMILY NOTES: DS39689F-page 94 © 2009 Microchip Technology Inc. ...
Page 95
... PIC18F2221/2321/4221/4321 FAMILY 9 HARDWARE MULTIPLIER 9.1 Introduction All PIC18 devices include hardware multiplier as part of the ALU. The multiplier performs an unsigned operation and yields a 16-bit result that is stored in the product register pair, PRODH:PRODL. The multiplier’s operation does not affect any flags in the STATUS register ...
Page 96
... PIC18F2221/2321/4221/4321 FAMILY Example 9-3 shows the sequence unsigned multiplication. Equation 9-1 shows the algorithm that is used. The 32-bit result is stored in four registers (RES3:RES0). EQUATION 9- UNSIGNED MULTIPLICATION ALGORITHM RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L 16 = (ARG1H • ARG2H • (ARG1H • ARG2L • (ARG1L • ARG2H • (ARG1L • ...
Page 97
... PIC18F2221/2321/4221/4321 FAMILY 10.0 INTERRUPTS The PIC18F2221/2321/4221/4321 family devices have multiple interrupt sources and an interrupt priority feature that allows most interrupt sources to be assigned a high-priority level or a low-priority level. The high-priority interrupt vector is at 0008h and the low- priority interrupt vector is at 0018h. High-priority interrupt events will interrupt any low-priority interrupts that may be in progress ...
Page 98
... PIC18F2221/2321/4221/4321 FAMILY FIGURE 10-1: PIC18 INTERRUPT LOGIC SSPIF SSPIE SSPIP ADIF ADIE ADIP RCIF RCIE RCIP Additional Peripheral Interrupts High-Priority Interrupt Generation Low-Priority Interrupt Generation SSPIF SSPIE SSPIP ADIF ADIE ADIP RCIF RCIE RCIP Additional Peripheral Interrupts DS39689F-page 98 TMR0IF TMR0IE TMR0IP ...
Page 99
... PIC18F2221/2321/4221/4321 FAMILY 10.1 INTCON Registers The INTCON registers are readable and writable registers, which contain various enable, priority and flag bits. REGISTER 10-1: INTCON: INTERRUPT CONTROL REGISTER R/W-0 GIE/GIEH PEIE/GIEL bit 7 bit 7 GIE/GIEH: Global Interrupt Enable bit When IPEN = Enables all unmasked interrupts ...
Page 100
... PIC18F2221/2321/4221/4321 FAMILY REGISTER 10-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 RBPU INTEDG0 bit 7 bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG0: External Interrupt 0 Edge Select bit 1 = Interrupt on rising edge ...
Page 101
... PIC18F2221/2321/4221/4321 FAMILY REGISTER 10-3: INTCON3: INTERRUPT CONTROL REGISTER 3 R/W-1 R/W-1 INT2IP INT1IP bit 7 bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 Unimplemented: Read as ‘0’ bit 4 ...
Page 102
... PIC18F2221/2321/4221/4321 FAMILY 10.2 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Request (Flag) registers (PIR1 and PIR2). REGISTER 10-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 ...
Page 103
... PIC18F2221/2321/4221/4321 FAMILY REGISTER 10-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 R/W-0 R/W-0 OSCFIF CMIF bit 7 bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit 1 = Device oscillator failed, clock input has changed to INTOSC (must be cleared in software Device clock operating bit 6 CMIF: Comparator Interrupt Flag bit ...
Page 104
... PIC18F2221/2321/4221/4321 FAMILY 10.3 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of periph- eral interrupt sources, there are two Peripheral Interrupt Enable registers (PIE1 and PIE2). When IPEN = 0, the PEIE bit must be set to enable any of these peripheral interrupts ...
Page 105
... PIC18F2221/2321/4221/4321 FAMILY REGISTER 10-7: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 R/W-0 OSCFIE CMIE bit 7 bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 CMIE: Comparator Interrupt Enable bit 1 = Enabled 0 = Disabled bit 5 Unimplemented: Read as ‘0’ bit 4 EEIE: Data EEPROM/Flash Write Operation Interrupt Enable bit ...
Page 106
... PIC18F2221/2321/4221/4321 FAMILY 10.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of periph- eral interrupt sources, there are two Peripheral Interrupt Priority registers (IPR1 and IPR2). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set ...
Page 107
... PIC18F2221/2321/4221/4321 FAMILY REGISTER 10-9: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 R/W-1 R/W-1 OSCFIP CMIP bit 7 bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 CMIP: Comparator Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 Unimplemented: Read as ‘0’ bit 4 ...
Page 108
... PIC18F2221/2321/4221/4321 FAMILY 10.5 RCON Register The RCON register contains flag bits which are used to determine the cause of the last Reset or wake-up from Idle or Sleep modes. RCON also contains the IPEN bit which enables interrupt priorities. REGISTER 10-10: RCON: RESET CONTROL REGISTER ...
Page 109
... PIC18F2221/2321/4221/4321 FAMILY 10.6 INTx Pin Interrupts External interrupts on the RB0/INT0, RB1/INT1 and RB2/INT2 pins are edge-triggered. If the corresponding INTEDGx bit in the INTCON2 register is set (= 1), the interrupt is triggered by a rising edge; if the bit is clear, the trigger is on the falling edge. When a valid edge appears on the RBx/INTx pin, the corresponding flag bit, INTxF, is set ...
Page 110
... PIC18F2221/2321/4221/4321 FAMILY NOTES: DS39689F-page 110 © 2009 Microchip Technology Inc. ...
Page 111
... PIC18F2221/2321/4221/4321 FAMILY 11.0 I/O PORTS Depending on the device selected and features enabled, there are up to five ports available. Some pins of the I/O ports are multiplexed with an alternate function from the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin ...
Page 112
... PIC18F2221/2321/4221/4321 FAMILY TABLE 11-1: PORTA I/O SUMMARY TRIS Pin Function Setting RA0/AN0 RA0 0 1 AN0 1 RA1/AN1 RA1 0 1 AN1 1 RA2/AN2/ RA2 0 V -/CV REF REF 1 AN2 REF CV x REF RA3/AN3/V + RA3 0 REF 1 AN3 REF RA4/T0CKI/C1OUT RA4 0 1 T0CKI 1 C1OUT 0 RA5/AN4/SS/ RA5 0 HLVDIN/C2OUT ...
Page 113
... PIC18F2221/2321/4221/4321 FAMILY TABLE 11-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Name Bit 7 Bit 6 (1) (1) PORTA RA7 RA6 (1) (1) LATA LATA7 LATA6 (1) (1) TRISA TRISA7 TRISA6 ADCON1 — — CMCON C2OUT C1OUT CVRCON CVREN CVROE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. ...
Page 114
... PIC18F2221/2321/4221/4321 FAMILY 11.2 PORTB, TRISB and LATB Registers PORTB is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i ...
Page 115
... PIC18F2221/2321/4221/4321 FAMILY TABLE 11-3: PORTB I/O SUMMARY TRIS Pin Function Setting RB0/INT0/FLT0/ RB0 0 AN12 1 INT0 1 FLT0 1 AN12 1 RB1/INT1/AN10 RB1 0 1 INT1 1 AN10 1 RB2/INT2/AN8 RB2 0 1 INT2 1 AN8 1 RB3/AN9/CCP2 RB3 0 1 AN9 1 (2) CCP2 0 1 RB4/KBI0/AN11 RB4 0 1 KBI0 1 AN11 1 RB5/KBI1/PGM RB5 ...
Page 116
... PIC18F2221/2321/4221/4321 FAMILY TABLE 11-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Name Bit 7 Bit 6 PORTB RB7 RB6 LATB PORTB Data Latch Register (Read and Write to Data Latch) TRISB PORTB Data Direction Register INTCON GIE/GIEH PEIE/GIEL TMR0IE INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTCON3 INT2IP ...
Page 117
... PIC18F2221/2321/4221/4321 FAMILY 11.3 PORTC, TRISC and LATC Registers PORTC is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISC. Set- ting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i ...
Page 118
... PIC18F2221/2321/4221/4321 FAMILY TABLE 11-5: PORTC I/O SUMMARY TRIS Pin Function Setting RC0/T1OSO/ RC0 0 T13CKI 1 T1OSO x T13CKI 1 RC1/T1OSI/CCP2 RC1 0 1 T1OSI x (1) CCP2 0 1 RC2/CCP1/P1A RC2 0 1 CCP1 0 1 (2) P1A 0 RC3/SCK/SCL RC3 0 1 SCK 0 1 SCL 0 1 RC4/SDI/SDA RC4 0 1 SDI 1 SDA ...
Page 119
... PIC18F2221/2321/4221/4321 FAMILY TABLE 11-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Name Bit 7 Bit 6 PORTC RC7 RC6 LATC PORTC Data Latch Register (Read and Write to Data Latch) TRISC PORTC Data Direction Register © 2009 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 RC5 RC4 ...
Page 120
... PIC18F2221/2321/4221/4321 FAMILY 11.4 PORTD, TRISD and LATD Registers Note: PORTD is only available on 40/44-pin devices. PORTD is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISD. Set- ting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a High-Impedance mode) ...
Page 121
... PIC18F2221/2321/4221/4321 FAMILY TABLE 11-7: PORTD I/O SUMMARY TRIS Pin Function Setting RD0/PSP0 RD0 0 1 PSP0 x x RD1/PSP1 RD1 0 1 PSP1 x x RD2/PSP2 RD2 0 1 PSP2 x x RD3/PSP3 RD3 0 1 PSP3 x x RD4/PSP4 RD4 0 1 PSP4 x x RD5/PSP5/P1B RD5 0 1 PSP5 x x P1B ...
Page 122
... PIC18F2221/2321/4221/4321 FAMILY TABLE 11-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Name Bit 7 Bit 6 PORTD RD7 RD6 LATD PORTD Data Latch Register (Read and Write to Data Latch) TRISD PORTD Data Direction Register TRISE IBF OBF CCP1CON P1M1 P1M0 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTD. ...
Page 123
... PIC18F2221/2321/4221/4321 FAMILY 11.5 PORTE, TRISE and LATE Registers Depending on the particular PIC18F2221/2321/4221/ 4321 family device selected, PORTE is implemented in two different ways. For 40/44-pin devices, PORTE is a 4-bit wide port. Three pins (RE0/RD/AN5, RE1/WR/AN6 and RE2/CS/ AN7) are individually configurable as inputs or outputs. ...
Page 124
... PIC18F2221/2321/4221/4321 FAMILY REGISTER 11-1: TRISE REGISTER (40/44-PIN DEVICES ONLY) R-0 IBF OBF bit 7 bit 7 IBF: Input Buffer Full Status bit word has been received and waiting to be read by the CPU word has been received bit 6 OBF: Output Buffer Full Status bit ...
Page 125
... PIC18F2221/2321/4221/4321 FAMILY TABLE 11-9: PORTE I/O SUMMARY TRIS Pin Function Setting RE0/RD/AN5 RE0 AN5 1 RE1/WR/AN6 RE1 AN6 1 RE2/CS/AN7 RE2 AN7 1 (1) MCLR/V /RE3 MCLR — — PP (2) RE3 — Legend: DIG = Digital level output; TTL = TTL input buffer Schmitt Trigger input buffer; ANA = Analog level input/output; ...
Page 126
... PIC18F2221/2321/4221/4321 FAMILY 11.6 Parallel Slave Port Note: The Parallel Slave Port is only available on 40/44-pin devices. In addition to its function as a general I/O port, PORTD can also operate as an 8-bit wide Parallel Slave Port (PSP) or microprocessor port. PSP operation is controlled by the 4 upper bits of the TRISE register (Register 11-1) ...
Page 127
... PIC18F2221/2321/4221/4321 FAMILY FIGURE 11-3: PARALLEL SLAVE PORT WRITE WAVEFORMS PORTD<7:0> IBF OBF PSPIF FIGURE 11-4: PARALLEL SLAVE PORT READ WAVEFORMS PORTD<7:0> IBF OBF PSPIF TABLE 11-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Name Bit 7 Bit 6 PORTD RD7 RD6 LATD PORTD Data Latch Register (Read and Write to Data Latch) ...
Page 128
... PIC18F2221/2321/4221/4321 FAMILY NOTES: DS39689F-page 128 © 2009 Microchip Technology Inc. ...
Page 129
... PIC18F2221/2321/4221/4321 FAMILY 12.0 TIMER0 MODULE The Timer0 module incorporates the following features: • Software selectable operation as a timer or coun- ter in both 8-bit or 16-bit modes • Readable and writable registers • Dedicated 8-bit, software programmable prescaler • Selectable clock source (internal or external) • ...
Page 130
... PIC18F2221/2321/4221/4321 FAMILY 12.1 Timer0 Operation Timer0 can operate as either a timer or a counter; the mode is selected with the T0CS bit (T0CON<5>). In Timer mode (T0CS = 0), the module increments on every clock by default unless a different prescaler value is selected (see Section 12.3 “Prescaler”). If the TMR0 register is written to, the increment is inhibited for the following two instruction cycles ...
Page 131
... PIC18F2221/2321/4221/4321 FAMILY 12.3 Prescaler An 8-bit counter is available as a prescaler for the Timer0 module. The prescaler is not directly readable or writable; its value is set by the PSA and T0PS<2:0> bits (T0CON<3:0>) which determine assignment and prescale ratio. Clearing the PSA bit assigns the prescaler to the Timer0 module ...
Page 132
... PIC18F2221/2321/4221/4321 FAMILY NOTES: DS39689F-page 132 © 2009 Microchip Technology Inc. ...
Page 133
... PIC18F2221/2321/4221/4321 FAMILY 13.0 TIMER1 MODULE The Timer1 timer/counter module incorporates these features: • Software selectable operation as a 16-bit timer or counter • Readable and writable 8-bit registers (TMR1H and TMR1L) • Selectable clock source (internal or external) with device clock or Timer1 oscillator internal options • ...
Page 134
... PIC18F2221/2321/4221/4321 FAMILY 13.1 Timer1 Operation Timer1 can operate in one of these modes: • Timer • Synchronous Counter • Asynchronous Counter The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). When TMR1CS is cleared (= 0), Timer1 increments on every internal instruction FIGURE 13-1: TIMER1 BLOCK DIAGRAM ...
Page 135
... PIC18F2221/2321/4221/4321 FAMILY 13.2 Timer1 16-Bit Read/Write Mode Timer1 can be configured for 16-bit reads and writes (see Figure 13-2). When the RD16 control bit (T1CON<7>) is set, the address for TMR1H is mapped to a buffer register for the high byte of Timer1. A read from TMR1L will load the contents of the high byte of Timer1 into the Timer1 high byte buffer ...
Page 136
... PIC18F2221/2321/4221/4321 FAMILY 13.3.3 TIMER1 OSCILLATOR LAYOUT CONSIDERATIONS The Timer1 oscillator circuit draws very little power during operation. Due to the low-power nature of the oscillator, it may also be sensitive to rapidly changing signals in close proximity. The oscillator circuit, shown in Figure 13-3, should be located as close as possible to the microcontroller. ...
Page 137
... PIC18F2221/2321/4221/4321 FAMILY EXAMPLE 13-1: IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE RTCinit MOVLW 80h MOVWF TMR1H CLRF TMR1L MOVLW b'00001111' MOVWF T1CON CLRF secs CLRF mins MOVLW .12 MOVWF hours BSF PIE1, TMR1IE RETURN RTCisr BSF TMR1H, 7 BCF PIR1, TMR1IF INCF secs, F MOVLW ...
Page 138
... PIC18F2221/2321/4221/4321 FAMILY NOTES: DS39689F-page 138 © 2009 Microchip Technology Inc. ...
Page 139
... PIC18F2221/2321/4221/4321 FAMILY 14.0 TIMER2 MODULE The Timer2 timer module incorporates the following features: • 8-bit timer and period registers (TMR2 and PR2, respectively) • Readable and writable (both registers) • Software programmable prescaler (1:1, 1:4 and 1:16) • Software programmable postscaler (1:1 through 1:16) • ...
Page 140
... PIC18F2221/2321/4221/4321 FAMILY 14.2 Timer2 Interrupt Timer2 can also generate an optional device interrupt. The Timer2 output signal (TMR2 to PR2 match) provides the input for the 4-bit output counter/post- scaler. This counter generates the TMR2 match inter- rupt flag which is latched in TMR2IF (PIR1<1>). The interrupt is enabled by setting the TMR2 Match Inter- rupt Enable bit, TMR2IE (PIE1< ...
Page 141
... PIC18F2221/2321/4221/4321 FAMILY 15.0 TIMER3 MODULE The Timer3 timer/counter module incorporates these features: • Software selectable operation as a 16-bit timer or counter • Readable and writable 8-bit registers (TMR3H and TMR3L) • Selectable clock source (internal or external) with device clock or Timer1 oscillator internal options • ...
Page 142
... PIC18F2221/2321/4221/4321 FAMILY 15.1 Timer3 Operation Timer3 can operate in one of three modes: • Timer • Synchronous Counter • Asynchronous Counter FIGURE 15-1: TIMER3 BLOCK DIAGRAM (8-BIT READ/WRITE MODE) Timer1 Oscillator T1OSO/T13CKI T1OSI (1) T1OSCEN T3CKPS<1:0> T3SYNC TMR3ON CCP1/CCP2 Special Event Trigger CCP1/CCP2 Select from T3CON<6,3> ...
Page 143
... PIC18F2221/2321/4221/4321 FAMILY 15.2 Timer3 16-Bit Read/Write Mode Timer3 can be configured for 16-bit reads and writes (see Figure 15-2). When the RD16 control bit (T3CON<7>) is set, the address for TMR3H is mapped to a buffer register for the high byte of Timer3. A read from TMR3L will load the contents of the high byte of Timer3 into the Timer3 High Byte Buffer register ...
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... PIC18F2221/2321/4221/4321 FAMILY NOTES: DS39689F-page 144 © 2009 Microchip Technology Inc. ...
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... PIC18F2221/2321/4221/4321 FAMILY 16.0 CAPTURE/COMPARE/PWM (CCP) MODULES PIC18F2221/2321/4221/4321 family devices all have two CCP (Capture/Compare/PWM) modules. Each module contains a 16-bit register which can operate as a 16-bit Capture register, a 16-bit Compare register or a PWM Master/Slave Duty Cycle register. In 28-pin devices, the two standard CCP modules (CCP1 and CCP2) operate as described in this chapter ...
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... PIC18F2221/2321/4221/4321 FAMILY 16.1 CCP Module Configuration Each Capture/Compare/PWM module is associated with a control register (generically, CCPxCON) and a data register (CCPRx). The data register, in turn, is comprised of two 8-bit registers: CCPRxL (low byte) and CCPRxH (high byte). All registers are both readable and writable. ...
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... PIC18F2221/2321/4221/4321 FAMILY 16.2 Capture Mode In Capture mode, the CCPRxH:CCPRxL register pair captures the 16-bit value of the TMR1 or TMR3 registers when an event occurs on the corresponding CCPx pin. An event is defined as one of the following: • every falling edge • every rising edge • every 4th rising edge • ...
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... PIC18F2221/2321/4221/4321 FAMILY 16.3 Compare Mode In Compare mode, the 16-bit CCPRx register value is constantly compared against either the TMR1 or TMR3 register pair value. When a match occurs, the CCPx pin can be: • driven high • driven low • toggled (high-to-low or low-to-high) • remain unchanged (that is, reflects the state of the ...
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... PIC18F2221/2321/4221/4321 FAMILY TABLE 16-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3 Name Bit 7 Bit 6 INTCON GIE/GIEH PEIE/GIEL TMR0IE (1) RCON IPEN SBOREN (2) PIR1 PSPIF ADIF (2) PIE1 PSPIE ADIE (2) IPR1 PSPIP ADIP PIR2 OSCFIF CMIF PIE2 OSCFIE CMIE IPR2 OSCFIP CMIP TRISB ...
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... PIC18F2221/2321/4221/4321 FAMILY 16.4 PWM Mode In Pulse-Width Modulation (PWM) mode, the CCPx pin produces 10-bit resolution PWM output. Since the CCP2 pin is multiplexed with a PORTB or PORTC data latch, the appropriate TRIS bit must be cleared to make the CCP2 pin an output. Note: Clearing the CCP2CON register will force ...
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... PIC18F2221/2321/4221/4321 FAMILY The CCPRxH register and a 2-bit internal latch are used to double-buffer the PWM duty cycle. This double-buffering is essential for glitchless PWM operation. When the CCPRxH and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock or 2 bits of the TMR2 prescaler, the CCPx pin is cleared. ...
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... PIC18F2221/2321/4221/4321 FAMILY TABLE 16-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2 Name Bit 7 Bit 6 INTCON GIE/GIEH PEIE/GIEL (1) RCON IPEN SBOREN (2) PIR1 PSPIF ADIF (2) PIE1 PSPIE ADIE (2) IPR1 PSPIP ADIP TRISB PORTB Data Direction Register TRISC PORTC Data Direction Register TMR2 Timer2 Register ...
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... ECCP module are the same as described for the standard CCP module. The control register for the Enhanced CCP module is shown in Register 17-1. It differs from the CCPxCON registers in PIC18F2221/2321 devices in that the two Most Significant bits are implemented to control PWM functionality. R/W-0 ...
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... PIC18F2221/2321/4221/4321 FAMILY In addition to the expanded range of modes available through the CCP1CON and ECCP1AS registers, the ECCP module has an additional register associated with Enhanced PWM operation and auto-shutdown features; it is: • ECCP1DEL (PWM Dead-Band Delay) 17.1 ECCP Outputs and Configuration The Enhanced CCP module may have up to four PWM outputs, depending on the selected operating mode ...
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... PIC18F2221/2321/4221/4321 FAMILY 17.4 Enhanced PWM Mode The Enhanced PWM mode provides additional PWM output options for a broader range of control applica- tions. The module is a backward compatible version of the standard CCP module and offers up to four outputs, designated P1A through P1D. Users are also able to select the polarity of the signal (either active-high or active-low). The module’ ...
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... PIC18F2221/2321/4221/4321 FAMILY 17.4.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits 10-bit resolution is available. The CCPR1L contains the eight MSbs and the CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The PWM duty cycle is calculated by the following equation ...
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... PIC18F2221/2321/4221/4321 FAMILY FIGURE 17-2: PWM OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) SIGNAL CCP1CON <7:6> P1A Modulated (Single Output) 00 P1A Modulated (Half-Bridge) 10 P1B Modulated P1A Active (Full-Bridge, P1B Inactive 01 Forward) P1C Inactive P1D Modulated P1A Inactive P1B Modulated (Full-Bridge, 11 Reverse) P1C Active P1D Inactive ...
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... PIC18F2221/2321/4221/4321 FAMILY 17.4.4 HALF-BRIDGE MODE In the Half-Bridge Output mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the P1A pin, while the complementary PWM output signal is output on the P1B pin (Figure 17-4). This mode can be used for half-bridge applications, as shown ...
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... PIC18F2221/2321/4221/4321 FAMILY 17.4.5 FULL-BRIDGE MODE In Full-Bridge Output mode, four pins are used as outputs; however, only two outputs are active at a time. In the Forward mode, pin P1A is continuously active and pin P1D is modulated. In the Reverse mode, pin P1C is continuously active and pin P1B is modulated. ...
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... PIC18F2221/2321/4221/4321 FAMILY FIGURE 17-7: EXAMPLE OF FULL-BRIDGE APPLICATION PIC18F4X21 P1A P1B P1C P1D 17.4.5.1 Direction Change in Full-Bridge Mode In the Full-Bridge Output mode, the P1M1 bit in the CCP1CON register allows user to control the forward/ reverse direction. When the application firmware changes this direction control bit, the module will assume the new direction on the next PWM cycle ...
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... PIC18F2221/2321/4221/4321 FAMILY FIGURE 17-8: PWM DIRECTION CHANGE SIGNAL P1A (Active-High) P1B (Active-High) P1C (Active-High) P1D (Active-High) DC Note 1: The direction bit in the CCP1 Control register (CCP1CON<7>) is written any time during the PWM cycle. 2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle at intervals ...
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... PIC18F2221/2321/4221/4321 FAMILY 17.4.6 PROGRAMMABLE DEAD-BAND DELAY Note: Programmable dead-band delay is not implemented in 28-pin devices with standard CCP modules. In half-bridge applications, where all power switches are modulated at the PWM frequency at all times, the power switches normally require more time to turn off than to turn on. If both the upper and lower power ...
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... PIC18F2221/2321/4221/4321 FAMILY REGISTER 17-3: ECCP1AS: ENHANCED CAPTURE/COMPARE/PWM AUTO-SHUTDOWN CONTROL REGISTER R/W-0 R/W-0 ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 bit 7 bit 7 ECCPASE: ECCP Auto-Shutdown Event Status bit shutdown event has occurred; ECCP outputs are in shutdown state 0 = ECCP outputs are operating bit 6-4 ECCPAS< ...
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... PIC18F2221/2321/4221/4321 FAMILY 17.4.7.1 Auto-Shutdown and Automatic Restart The auto-shutdown feature can be configured to allow automatic restarts of the module following a shutdown event. This is enabled by setting the PRSEN bit of the ECCP1DEL register (ECCP1DEL<7>). In Shutdown mode with PRSEN = 1 (Figure 17-10), the ECCPASE bit will remain set for as long as the cause of the shutdown continues ...
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... PIC18F2221/2321/4221/4321 FAMILY 17.4.9 SETUP FOR PWM OPERATION The following steps should be taken when configuring the ECCP module for PWM operation: 1. Configure the PWM pins, P1A and P1B (and P1C and P1D, if used), as inputs by setting the corresponding TRIS bits. 2. Set the PWM period by loading the PR2 register. ...
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... PIC18F2221/2321/4221/4321 FAMILY TABLE 17-3: REGISTERS ASSOCIATED WITH ECCP1 MODULE AND TIMER1 TO TIMER3 Name Bit 7 Bit 6 INTCON GIE/GIEH PEIE/GIEL (1) RCON IPEN SBOREN (2) PIR1 PSPIF ADIF (2) PIE1 PSPIE ADIE (2) IPR1 PSPIP ADIP PIR2 OSCFIF CMIF PIE2 OSCFIE CMIE IPR2 OSCFIP CMIP TRISB PORTB Data Direction Register ...
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... PIC18F2221/2321/4221/4321 FAMILY 18.0 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE 18.1 Master SSP (MSSP) Module Overview The Master Synchronous Serial Port (MSSP) module is a serial interface, useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc ...
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... PIC18F2221/2321/4221/4321 FAMILY 18.3.1 REGISTERS The MSSP module has four registers for SPI mode operation. These are: • MSSP Control Register 1 (SSPCON1) • MSSP Status Register (SSPSTAT) • Serial Receive/Transmit Buffer Register (SSPBUF) • MSSP Shift Register (SSPSR) – Not directly accessible SSPCON1 and SSPSTAT are the control and status registers in SPI mode operation ...
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... PIC18F2221/2321/4221/4321 FAMILY REGISTER 18-2: SSPCON1: MSSP CONTROL REGISTER 1 (SPI MODE) R/W-0 R/W-0 WCOL SSPOV bit 7 bit 7 WCOL: Write Collision Detect bit (Transmit mode only The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software collision bit 6 SSPOV: Receive Overflow Indicator bit SPI Slave mode new byte is received while the SSPBUF register is still holding the previous data ...
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... PIC18F2221/2321/4221/4321 FAMILY 18.3.2 OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPCON1<5:0> and SSPSTAT<7:6>). These control bits allow the following to be specified: • Master mode (SCK is the clock output) • Slave mode (SCK is the clock input) • ...
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... PIC18F2221/2321/4221/4321 FAMILY 18.3.3 ENABLING SPI I/O To enable the serial port, MSSP Enable bit, SSPEN (SSPCON1<5>), must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, reinitialize the SSPCON registers and then set the SSPEN bit. This configures the SDI, SDO, SCK and SS pins as serial port pins ...
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... PIC18F2221/2321/4221/4321 FAMILY 18.3.5 MASTER MODE The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor 2, Figure 18- broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI operation is only going to receive, the SDO output could be disabled (programmed as an input) ...
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... PIC18F2221/2321/4221/4321 FAMILY 18.3.6 SLAVE MODE In Slave mode, the data is transmitted and received as the external clock pulses appear on SCK. When the last bit is latched, the SSPIF interrupt flag bit is set. Before enabling the module in SPI Slave mode, the clock line must match the proper Idle state. The clock line can be observed by reading the SCK pin. The Idle state is determined by the CKP bit (SSPCON1< ...
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... PIC18F2221/2321/4221/4321 FAMILY FIGURE 18-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit 7 SDI (SMP = 0) bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF FIGURE 18-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) ...
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... PIC18F2221/2321/4221/4321 FAMILY 18.3.8 OPERATION IN POWER-MANAGED MODES In SPI Master mode, module clocks may be operating at a different speed than when in full power mode. In the case of Sleep mode, all clocks are halted. In Idle modes, a clock is provided to the peripherals. That clock should be from the primary clock source, the secondary clock (Timer1 oscillator at 32.768 kHz) or the INTOSC source. See Section 3.7 “ ...
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... PIC18F2221/2321/4221/4321 FAMILY 2 18 Mode 2 The MSSP module mode fully implements all master and slave functions (including general call support) and provides interrupts on Start and Stop bits in hardware to determine a free bus (multi-master function). The MSSP module implements the standard mode specifications, as well as 7-bit and 10-bit addressing ...
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... PIC18F2221/2321/4221/4321 FAMILY REGISTER 18-3: SSPSTAT: MSSP STATUS REGISTER (I R/W-0 R/W-0 SMP bit 7 bit 7 SMP: Slew Rate Control bit In Master or Slave mode Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz Slew rate control enabled for High-Speed mode (400 kHz) ...
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... PIC18F2221/2321/4221/4321 FAMILY REGISTER 18-4: SSPCON1: MSSP CONTROL REGISTER 1 (I R/W-0 R/W-0 WCOL SSPOV bit 7 bit 7 WCOL: Write Collision Detect bit In Master Transmit mode write to the SSPBUF register was attempted while the I a transmission to be started (must be cleared in software collision In Slave Transmit mode: ...
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... PIC18F2221/2321/4221/4321 FAMILY REGISTER 18-5: SSPCON2: MSSP CONTROL REGISTER 2 (I R/W-0 R/W-0 GCEN ACKSTAT bit 7 bit 7 GCEN: General Call Enable bit (Slave mode only Enable interrupt when a general call address (0000h) is received in the SSPSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit (Master Transmit mode only) ...
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... PIC18F2221/2321/4221/4321 FAMILY REGISTER 18-5: SSPCON2: MSSP CONTROL REGISTER 2 (I R/W-0 R/W-0 GCEN ACKSTAT bit 7 bit 0 SEN: Start Condition Enable/Stretch Enable bit In Master mode Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware Start condition Idle In Slave mode Clock stretching is enabled for both slave transmit and slave receive (stretch enabled) ...
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... PIC18F2221/2321/4221/4321 FAMILY 18.4.2 OPERATION The MSSP module functions are enabled by setting MSSP Enable bit, SSPEN (SSPCON1<5>). The SSPCON1 register allows control of the I operation. Four mode selection bits (SSPCON1<3:0>) 2 allow one of the following I C modes to be selected: 2 • Master mode clock 2 • I ...
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... PIC18F2221/2321/4221/4321 FAMILY 18.4.3.2 Address Masking Masking an address bit causes that bit to become a “don’t care”. When one address bit is masked, two addresses will be Acknowledged and cause an inter- rupt possible to mask more than one address bit at a time, which makes it possible to Acknowledge up to ...
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... PIC18F2221/2321/4221/4321 FAMILY 18.4.3.3 Reception When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register and the SDA line is held low (ACK). When the address byte overflow condition exists, then the no Acknowledge (ACK) pulse is given. An overflow condition is defined as either bit BF (SSPSTAT< ...
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... PIC18F2221/2321/4221/4321 FAMILY 2 FIGURE 18-8: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESSING) DS39689F-page 184 © 2009 Microchip Technology Inc. ...
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... PIC18F2221/2321/4221/4321 FAMILY 2 FIGURE 18-9: I C™ SLAVE MODE TIMING WITH SEN = 0 AND ADMSK<5:1> = 01011 (RECEPTION, 7-BIT ADDRESSING) © 2009 Microchip Technology Inc. DS39689F-page 185 ...
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... PIC18F2221/2321/4221/4321 FAMILY 2 FIGURE 18-10: I C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESSING) DS39689F-page 186 © 2009 Microchip Technology Inc. ...
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... PIC18F2221/2321/4221/4321 FAMILY 2 FIGURE 18-11: I C™ SLAVE MODE TIMING WITH SEN = 0 AND ADMSK = 01001 (RECEPTION, 10-BIT ADDRESSING) © 2009 Microchip Technology Inc. DS39689F-page 187 ...
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... PIC18F2221/2321/4221/4321 FAMILY 2 FIGURE 18-12: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESSING) DS39689F-page 188 © 2009 Microchip Technology Inc. ...
Page 189
... PIC18F2221/2321/4221/4321 FAMILY 2 FIGURE 18-13: I C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESSING) © 2009 Microchip Technology Inc. DS39689F-page 189 ...
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... PIC18F2221/2321/4221/4321 FAMILY 18.4.4 CLOCK STRETCHING Both 7-Bit and 10-Bit Slave modes implement automatic clock stretching during a transmit sequence. The SEN bit (SSPCON2<0>) allows clock stretching to be enabled during receives. Setting SEN will cause the SCL pin to be held low at the end of each data receive sequence ...
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... PIC18F2221/2321/4221/4321 FAMILY 18.4.4.5 Clock Synchronization and the CKP bit When the CKP bit is cleared, the SCL output is forced to ‘0’. However, clearing the CKP bit will not assert the SCL output low until the SCL output is already sampled low. Therefore, the CKP bit will not assert the ...
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... PIC18F2221/2321/4221/4321 FAMILY 2 FIGURE 18-15: I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESSING) DS39689F-page 192 © 2009 Microchip Technology Inc. ...
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... PIC18F2221/2321/4221/4321 FAMILY 2 FIGURE 18-16: I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESSING) © 2009 Microchip Technology Inc. DS39689F-page 193 ...
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... PIC18F2221/2321/4221/4321 FAMILY 18.4.5 GENERAL CALL ADDRESS SUPPORT 2 The addressing procedure for the I C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master. The exception is the general call address which can address all devices. When this address is used, all devices should, in theory, respond with an Acknowledge ...
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... PIC18F2221/2321/4221/4321 FAMILY 18.4.6 MASTER MODE Master mode is enabled by setting and clearing the appropriate SSPM bits in SSPCON1 and by setting the SSPEN bit. In Master mode, the SCL and SDA lines are manipulated by the MSSP hardware. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions ...
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... PIC18F2221/2321/4221/4321 FAMILY 2 18.4.6 Master Mode Operation The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I not be released ...
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... PIC18F2221/2321/4221/4321 FAMILY 18.4.7 BAUD RATE Master mode, the Baud Rate Generator (BRG) reload value is placed in the lower 7 bits of the SSPADD register (Figure 18-19). When a write occurs to SSPBUF, the Baud Rate Generator will automatically begin counting. The BRG counts down to 0 and stops until another reload has taken place ...
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... PIC18F2221/2321/4221/4321 FAMILY 18.4.7.1 Clock Arbitration Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, deasserts the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high ...
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... PIC18F2221/2321/4221/4321 FAMILY 2 18.4 MASTER MODE START CONDITION TIMING To initiate a Start condition, the user sets the Start Enable bit, SEN (SSPCON2<0>). If the SDA and SCL pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and starts its count. If SCL and SDA are both sampled high when the Baud Rate Generator times out (T pin is driven low ...
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... PIC18F2221/2321/4221/4321 FAMILY 2 18.4 MASTER MODE REPEATED START CONDITION TIMING A Repeated Start condition occurs when the RSEN bit (SSPCON2<1>) is programmed high and the I module is in the Idle state. When the RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sampled low, the Baud Rate Generator is loaded with the contents of SSPADD< ...