PIC18F43K22-E/P Microchip Technology, PIC18F43K22-E/P Datasheet - Page 260
PIC18F43K22-E/P
Manufacturer Part Number
PIC18F43K22-E/P
Description
8KB, Flash, 3968bytes-RAM,8-bit Family 40 PDIP .600in TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Specifications of PIC18F43K22-E/P
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 30x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
40-DIP (0.600", 15.24mm)
Processor Series
PIC18F
Core
PIC
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F43K22-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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PIC18(L)F2X/4XK22
REGISTER 15-4:
REGISTER 15-5:
DS41412D-page 260
bit 0
Note 1:
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7-1
bit 0
R/W-1
MSK7
2:
3:
For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPxOV is still
set when a new byte is received and BF = 1, but hardware continues to write the most recent byte to
SSPxBUF.
This bit has no effect in Slave modes for which Start and Stop condition detection is explicitly listed as
enabled.
The ACKTIM Status bit is active only when the AHEN bit or DHEN bit is set.
DHEN: Data Hold Enable bit (I
1 = Following the 8th falling edge of SCLx for a received data byte; slave hardware clears the CKP bit
0 = Data holding is disabled
MSK<7:1>: Mask bits
1 = The received address bit n is compared to SSPxADD<n> to detect I
0 = The received address bit n is not used to detect I
MSK<0>: Mask bit for I
I
1 = The received address bit 0 is compared to SSPxADD<0> to detect I
0 = The received address bit 0 is not used to detect I
I
2
2
C Slave mode, 10-bit address (SSPxM<3:0> = 0111 or 1111):
C Slave mode, 7-bit address, the bit is ignored
R/W-1
MSK6
of the SSPxCON1 register and SCLx is held low.
SSPxCON3: SSPx CONTROL REGISTER 3 (CONTINUED)
SSPxMSK: SSPx MASK REGISTER
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
R/W-1
MSK5
2
C Slave mode, 10-bit Address
2
C Slave mode only)
R/W-1
MSK4
Preliminary
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
R/W-1
MSK3
2
2
C address match
C address match
R/W-1
MSK2
2010 Microchip Technology Inc.
2
2
C address match
C address match
R/W-1
MSK1
R/W-1
MSK0
bit 0
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