PIC18F4458-I/ML Microchip Technology, PIC18F4458-I/ML Datasheet - Page 3
![24KB Flash, 2KB RAM, 256 Bytes EEPROM, 35 I/O, USB, 12bit ADC 44 QFN 8x8x0.9mm T](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC18F4458-I/ML
Manufacturer Part Number
PIC18F4458-I/ML
Description
24KB Flash, 2KB RAM, 256 Bytes EEPROM, 35 I/O, USB, 12bit ADC 44 QFN 8x8x0.9mm T
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2221-ISO.pdf
(46 pages)
2.PIC18F2458-ISO.pdf
(46 pages)
3.PIC18F2458-ISO.pdf
(6 pages)
4.PIC18F2458-ISO.pdf
(6 pages)
5.PIC18F2458-ISO.pdf
(6 pages)
Specifications of PIC18F4458-I/ML
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
24KB (12K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 13x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM163025 - PIC DEM FULL SPEED USB DEMO BRD444-1001 - DEMO BOARD FOR PICMICRO MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
7. Module: MSSP (SPI Slave)
© 2008 Microchip Technology Inc.
If configured in SPI Slave mode, the MSSP may not
successfully recognize data packets generated by an
external master processor. This applies to all SPI
Slave modes (CKE/CKP = 1 or 0), whether or not
slave select is enabled (SSPM3:SSPM0 = 010x).
Work around
Insert a series resistor between the SPI master
Serial Data Out (SDO) and the corresponding SPI
slave Serial Data In (SDI) input line of the
microcontroller. The required value for the resistor
varies with the application system’s characteristics
and
microcontrollers.
Experimentation
encouraged.
Date Codes that pertain to this issue:
All engineering and production devices.
the
process
and
variations
thorough
between
testing
PIC18F2458/2553/4458/4553
the
are
8. Module: MSSP
When operated in I
baud rate may be somewhat slower than predicted
by the following formula:
Work around
If the target application is sensitive to the baud rate
and requires more precision, the SSPADD value
can be adjusted to compensate.
If this work around is going to be used, it is recom-
mended that the firmware first check the Revision
ID by reading the DEVID1 value at address
3FFFFEh. Silicon revisions B6 and B7 will match
the I
Date Codes that pertain to this issue:
All engineering and production devices.
2
I
C baud rate predicted by the given formula.
2
C Master mode, clock
2
C™ Master mode, the I
=
--------------------------------------------- -
4
•
DS80323D-page 3
(
SSPADD
F
OSC
+
1
)
2
C