PIC18F6493T-I/PT Microchip Technology, PIC18F6493T-I/PT Datasheet - Page 38

• Manufacturer Part Number: PIC18F6493T-I/PT
• Description: PIC18F With 128-segment LCD Driver And 12-bit ADC, 16KB Flash, 768B RAM, CCP, MS
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F6493T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, LCD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: AUSART, EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164136, DM163030
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18F6493T-I/PTTR

PIC18F6393/6493/8393/8493
2.4
If the A/D is expected to operate while the device is in
a power-managed mode, the ACQT<2:0> and
ADCS<2:0> bits in ADCON2 should be updated in
accordance with the clock source to be used in that
mode. After entering the mode, an A/D acquisition or
conversion may be started. Once started, the device
should continue to be clocked by the same clock
source until the conversion has been completed.
If desired, the device may be placed into the
corresponding Idle mode during the conversion. If the
device clock frequency is less than 1 MHz, the A/D RC
clock source should be selected.
Operation in Sleep mode requires the A/D FRC clock to
be selected. If bits, ACQT<2:0>, are set to ‘000’ and a
conversion is started, the conversion will be delayed
one instruction cycle to allow execution of the SLEEP
instruction, and entry to Sleep mode. The IDLEN bit
(OSCCON<7>) must have already been cleared prior
to starting the conversion.
DS39896C-page 38
Operation in Power-Managed
Modes
2.5
The ADCON1, TRISA, TRISF and TRISH registers all
configure the A/D port pins. The port pins needed as
analog inputs must have their corresponding TRIS bits
set (input). If the TRIS bit is cleared (output), the digital
output level (V
The A/D operation is independent of the state of the
CHS<3:0> bits and the TRIS bits.
Note 1: When reading the PORT register, all pins
2: Analog levels on any pin defined as a dig-
Configuring Analog Port Pins
configured as analog input channels will
read as cleared (a low level). Analog con-
version on pins configured as digital pins
can be performed. The voltage on the pin
will be accurately converted.
ital input may cause the digital input buffer
to consume current out of the device’s
specification limits.
OH
or V
OL
 2010 Microchip Technology Inc.
) will be converted.