PIC18F6493T-I/PT Microchip Technology, PIC18F6493T-I/PT Datasheet - Page 39

• Manufacturer Part Number: PIC18F6493T-I/PT
• Description: PIC18F With 128-segment LCD Driver And 12-bit ADC, 16KB Flash, 768B RAM, CCP, MS
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F6493T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, LCD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: AUSART, EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164136, DM163030
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18F6493T-I/PTTR

2.6
Figure 2-4 shows the operation of the A/D Converter
after the GO/DONE bit has been set and the
ACQT<2:0> bits are cleared. A conversion is started
after the following instruction to allow entry into Sleep
mode before the conversion begins.
Figure 2-5 shows the operation of the A/D Converter
after the GO/DONE bit has been set, the ACQT<2:0>
bits are set to ‘010’ and a 4 T
been selected before the conversion starts.
Clearing the GO/DONE bit during a conversion will abort
the current conversion. The A/D Result register pair will
not be updated with the partially completed A/D
conversion sample. This means the ADRESH:ADRESL
registers will continue to contain the value of the last
completed conversion (or the last value written to the
ADRESH:ADRESL registers).
FIGURE 2-4:
FIGURE 2-5:
 2010 Microchip Technology Inc.
(Holding capacitor continues
acquiring input)
Set GO/DONE bit
T
Set GO/DONE bit
CY
Holding capacitor is disconnected from analog input (typically 100 ns)
1
– T
T
ACQT
A/D Conversions
Acquisition
AD
Automatic
2
Time
T
AD
Cycles
1 T
3
Conversion starts
b11
AD
A/D CONVERSION T
2 T
A/D CONVERSION T
4
AD
b10
1
3 T
AD
Conversion starts
(Holding capacitor is disconnected)
AD
b11
acquisition time has
b9
2
4 T
b10
AD
On the following cycle:
ADRESH:ADRESL are loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input
3
b8
5 T
On the following cycle:
ADRESH:ADRESL are loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input
PIC18F6393/6493/8393/8493
AD
AD
b9
AD
4
b7
6 T
CYCLES (ACQT<2:0> = 000, T
CYCLES (ACQT<2:0> = 010, T
b8
5
AD
b6
7 T
b7
T
6
AD
AD
b5
8
Cycles
After the A/D conversion is completed or aborted, a
2 T
be started. After this wait, acquisition on the selected
channel is automatically started.
2.7
The discharge phase is used to initialize the value of
the holding capacitor. The array is discharged before
every sample. This feature helps to optimize the unity
gain amplifier, as the circuit always needs to charge the
capacitor array, rather than charge/discharge based on
previous measure values.
b6
7
Note:
T
AD
AD
b4
wait is required before the next acquisition can
9 T
b5
8
Discharge
AD
b3
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
Code should wait at least 2 s after
enabling the A/D before beginning an
acquisition and conversion cycle.
10
b4
9
T
AD
b2
11
10
b3
ACQ
T
ACQ
AD
b1
11
b2
12
= 0)
= 4 T
T
AD
b0
12
b1
13
AD
)
DS39896C-page 39
T
Discharge
(typically 200 ns)
b0
13
AD
1
T
Discharge
(typically
200 ns)
AD
1