PIC18F65K22-E/PT Microchip Technology, PIC18F65K22-E/PT Datasheet - Page 313
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PIC18F65K22-E/PT
Manufacturer Part Number
PIC18F65K22-E/PT
Description
32kB Flash, 2kB RAM, 1kB EE, NanoWatt XLP, GP 64 TQFP 10x10x1mm TRAY
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F65K22-EMR.pdf
(550 pages)
Specifications of PIC18F65K22-E/PT
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
64-TQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F65K22-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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21.4.7
In I
reload value is placed in the lower 7 bits of the
SSPxADD register
occurs to SSPxBUF, the Baud Rate Generator will
automatically begin counting. The BRG counts down to
0 and stops until another reload has taken place. The
BRG count is decremented twice per instruction cycle
(T
BRG is reloaded automatically.
Once the given operation is complete (i.e., transmis-
sion of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCLx pin
will remain in its last state.
Table 21-3
instruction cycles and the BRG value loaded into
SSPxADD. The SSPxADD BRG value of 0x00 is not
supported.
FIGURE 21-19:
TABLE 21-3:
2009-2011 Microchip Technology Inc.
Note 1:
CY
2
C Master mode, the Baud Rate Generator (BRG)
) on the Q2 and Q4 clocks. In I
40 MHz
40 MHz
40 MHz
16 MHz
16 MHz
16 MHz
16 MHz
4 MHz
4 MHz
F
OSC
A minimum of 16 MHz F
BAUD RATE
demonstrates clock rates based on
I
2
C™ CLOCK RATE w/BRG
(Figure
BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM<3:0>
21-19). When a write
10 MHz
10 MHz
10 MHz
SCLx
4 MHz
4 MHz
4 MHz
1 MHz
1 MHz
4 MHz
F
2
CY
C Master mode, the
OSC
is required to get 1 MHz I
SSPM<3:0>
Reload
Control
CLKO
20 MHz
20 MHz
20 MHz
F
8 MHz
8 MHz
8 MHz
2 MHz
2 MHz
8 MHz
CY
* 2
Reload
PIC18F87K22 FAMILY
21.4.7.1
Because MSSP1 and MSSP2 are independent, they
can operate simultaneously in I
different baud rates. This is done by using different
BRG reload values for each module.
Because this mode derives its basic clock source from
the system clock, any changes to the clock will affect
both modules in the same proportion. It may be
possible to change one or both baud rates back to a
previous value by changing the BRG reload value.
BRG Down Counter
SSPxADD<6:0>
2
C.
BRG Value
Baud Rate and Module
Interdependence
0Ch
18h
1Fh
63h
09h
27h
02h
09h
03h
F
OSC
/4
(2 Rollovers of BRG)
2
C Master mode at
DS39960D-page 313
312.5 kHz
1 MHz
400 kHz
100 kHz
400 kHz
308 kHz
100 kHz
333 kHz
100 kHz
F
SCL
(1)
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