PIC18F67K90-E/MR Microchip Technology, PIC18F67K90-E/MR Datasheet - Page 260
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PIC18F67K90-E/MR
Manufacturer Part Number
PIC18F67K90-E/MR
Description
128kB Flash, 4kB RAM, 1kB EE, NanoWatt XLP, LCD 64 QFN 9x9x0.9mm TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F66K90-IMR.pdf
(570 pages)
Specifications of PIC18F67K90-E/MR
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
64-VFQFN Exposed Pad
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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PIC18F87K90 FAMILY
19.4.1
In Half-Bridge mode, two pins are used as outputs to
drive push-pull loads. The PWM output signal is output
on the PxA pin, while the complementary PWM output
signal is output on the PxB pin (see
mode can be used for half-bridge applications, as
shown in
where four power switches are being modulated with
two PWM signals.
In Half-Bridge mode, the programmable dead-band delay
can be used to prevent shoot-through current in
half-bridge power devices. The value of the PxDC<6:0>
bits of the ECCPxDEL register sets the number of
instruction cycles before the output is driven active. If the
value is greater than the duty cycle, the corresponding
output remains inactive during the entire cycle. For more
details on the dead-band delay operations, see
Section 19.4.6 “Programmable Dead-Band Delay
Mode”.
FIGURE 19-7:
DS39957D-page 260
Standard Half-Bridge Circuit (“Push-Pull”)
Half-Bridge Output Driving a Full-Bridge Circuit
Figure
HALF-BRIDGE MODE
19-7, or for full-bridge applications,
EXAMPLE OF HALF-BRIDGE APPLICATIONS
PxA
PxB
Figure
PxA
PxB
19-6). This
FET
Driver
FET
Driver
FET
Driver
FET
Driver
Since the PxA and PxB outputs are multiplexed with the
PORT data latches, the associated TRIS bits must be
cleared to configure PxA and PxB as outputs.
FIGURE 19-6:
Note 1: At this time, the TMR2 register is equal to the
PxA
PxB
td = Dead-Band Delay
(2)
(2)
Load
V+
2: Output signals are shown as active-high.
(1)
Pulse Width
PR2 register.
td
Load
Period
2009-2011 Microchip Technology Inc.
td
EXAMPLE OF
HALF-BRIDGE PWM
OUTPUT
FET
Driver
FET
Driver
+
-
+
-
(1)
Period
(1)
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