PIC18F67K90-E/MR Microchip Technology, PIC18F67K90-E/MR Datasheet - Page 386
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PIC18F67K90-E/MR
Manufacturer Part Number
PIC18F67K90-E/MR
Description
128kB Flash, 4kB RAM, 1kB EE, NanoWatt XLP, LCD 64 QFN 9x9x0.9mm TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F66K90-IMR.pdf
(570 pages)
Specifications of PIC18F67K90-E/MR
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
64-VFQFN Exposed Pad
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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PIC18F87K90 FAMILY
23.7
Figure 23-6
after the GO/DONE bit has been set and the
ACQT<2:0> bits are cleared. A conversion is started
after the following instruction to allow entry into Sleep
mode before the conversion begins.
Figure 23-7
after the GO/DONE bit has been set, the ACQT<2:0>
bits set to ‘ 010 ’ and a 4 T
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D Result register
pair will NOT be updated with the partially completed
A/D
FIGURE 23-6:
FIGURE 23-7:
DS39957D-page 386
Set GO/DONE bit
(Holding capacitor continues
acquiring input)
1
T
Set GO/DONE bit
conversion
CY
Holding capacitor is disconnected from analog input (typically 100 ns)
A/D Conversions
T
- T
Automatic
Acquisition
Time
ACQT
shows the operation of the A/D Converter
shows the operation of the A/D Converter
2
AD
Conversion starts
T
Cycles
AD
3
1
sample.
A/D CONVERSION T
A/D CONVERSION T
T
b11
AD
AD
4
2
acquisition time selected.
(Holding capacitor is disconnected)
Conversion starts
T
AD
b10
1
3
This
T
b11
AD
b9
2
Next Q4: ADRESH:ADRESL is loaded, GO/DONE bit is cleared,
4
Next Q4: ADRESH:ADRESL is loaded, GO/DONE bit is cleared,
means
T
b10
AD
3
b8
5
AD
AD
ADIF bit is set, holding capacitor is connected to analog input.
ADIF bit is set, holding capacitor is reconnected to analog input.
T
CYCLES (ACQT<2:0> = 000, T
CYCLES (ACQT<2:0> = 010, T
AD
the
b7
b9
4
6
T
AD
b6
5
b8
7
T
T
ADRESH:ADRESL registers will continue to contain
the value of the last completed conversion (or the last
value written to the ADRESH:ADRESL registers).
After the A/D conversion is completed or aborted, a
2 T
be started. After this Wait, acquisition on the selected
channel is automatically started.
AD
b7
AD
b5
6
Note:
AD
8
Cycles
Wait is required before the next acquisition can
T
b6
AD
7
b4
9 T
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
b5
AD
8
b3
10
2009-2011 Microchip Technology Inc.
T
b4
AD
9
b2
ACQ
ACQ
11
T
10
b3
AD
= 0)
= 4 T
b1
12
b2
T
AD
11
AD
b0
)
13
12
b1
13
b0
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