PIC18F86J50T-I/PT Microchip Technology, PIC18F86J50T-I/PT Datasheet - Page 4

• Manufacturer Part Number: PIC18F86J50T-I/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F86J50T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3904 B
• Interface Type: I2C, MSSP, SPI, EUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 65
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183022, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162087 - HEADER MPLAB ICD2 18F87J50 68/84MA180021 - MODULE PLUG-IN 18F87J50 FS USBAC164328 - MODULE SKT FOR 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18F86J50T-I/PTTR

PIC18F87J50 FAMILY
4. Module: MSSP
DS80481A-page 4
With MSSP1 or MSSP2 in SPI Master mode, the
F
CKE = 0, a write collision may occur if SSPBUF is
loaded immediately after the transfer is complete.
A delay may be required before writing SSPBUF,
after the MSSP Interrupt Flag bit (SSPIF) is set or
the Buffer Full bit (BF) is set. If the delay is
insufficiently short, a write collision may occur as
indicated by the WCOL bit being set.
Work around
Add a software delay of one SCK period after
detecting the completed transfer and prior to
updating the SSPBUF contents.
Affected Silicon Revisions
OSC
A2
X
/64 or Timer2/2 clock rate enabled and
A3
X
A4
X
5. Module: I/O (PORTH)
When the Parallel Master Port (PMP) module is
enabled (PMCONH<7> = 1) and the PMPMX bit
is clear (CONFIG3L<2> = 0), the PMP module
can, under certain conditions, override firmware
control over the RH0 and RH1 general purpose
I/O (GPIO) pins.
The RH0 and RH1 pins will function normally
and can still be used as standard GPIO if the
PMP is disabled or the PMPMX Configuration bit
is set.
This issue only applies to the 80-pin devices
(PIC18F85J50, PIC18F86J50, PIC18F86J55
and PIC18F87J50).
Work around
None.
Affected Silicon Revisions
A2
X
A3
X
A4
X
© 2009 Microchip Technology Inc.